Page 30 - Chip Scale Review_July August_2023-digital

Parallel validation strategies minimize debug time and

ensure sufficient test coverage

By Adir Zonta [Advantest]
T e s t d a t a v o l u m e s a r e test patterns generated manually from errors, analyze failing test patterns,

exploding as the number
of t r a n si s t or s p e r ch ip a test specification or automatically examine response traces, perform
debugging and diagnosis, and modify
using random or constraint-based test-
increases along with the number of test generation methods or other techniques the stimulus pattern, the expected
vectors needed to test each transistor. linked with EDA tools. Test patterns response pattern, or both. Alternatively,
A recent a r t icle [1] provided an from the EDA tools are generally in a automated tools can analyze failing test
overview of how the device validation standard format such as STIL (Standard patterns and generate reports making
and characterization, structural and Test Interface Language) or WGL recommendations for correcting errors
f unctional test at automated test (Waveform Generation Language). based on predefined rules.
equipment (ATE), and system-level Structural test patterns target specific
test have evolved over the years to deal fault models, such as “stuck at” faults Using automated parallel test
with ever-increasing complexity. The or timing faults, whereas functional stations to speed up the process
author [1] described how traditional test patterns aim to come closer to With or without automation, the
methods no longer suffice and introduced confirming the device under test’s process discussed above is time-
innovations in pre-silicon verification, (DUT) performance in its end use. consuming. Speeding up the process
first silicon bring-up, and post-silicon The need for functional test vectors is requires a test lab with the equipment
validation (PSV) that are necessary to particularly important in automotive necessar y to r un parallel patter n
meet today’s challenges. This article and other industries where performance validation, thereby minimizing the
provides more details on these recent and safety are critical. The following time spent on pattern debugging while
innovations and the systems necessary to sections discuss aspects of generating assuring sufficient test coverage. A
implement them, including information test patterns. solution such as the Advantest V93000
on how to equip an engineering lab with Cyclized test vectors. The patterns E X A Sca le E X Te st St at ion , a n
automated parallel test stations to speed in STIL or WGL from the EDA tools engineering platform for complex device
up test engineering tasks such as pattern must be converted to cyclized test bring-up that supports structural and
validation. In addition, it describes how vectors for the target ATE system. functional test, provides such parallel
a new standard helps bridge the gap The cyclization process involves test capability without requiring a lot
between the electronic design automation adding timing and control information of floor space because it is designed
(EDA) and ATE domains and how an to synchronize the patterns with a to fit under the company’s single-site
EDA company and an ATE maker have specific ATE system’s clock and control M4171 automated handler. Complete
collaborated on an initiative to put the signals, which can require extensive with integrated active thermal control
standard into practice. development time. (ATC) over a -45 to +125°C range,
Error causes. Inevitably, errors will the handler brings automated device
Test-pattern validation appear in the cyclized test vectors. loading, unloading, and binning into the
One of the challenges that the These errors could result from design laboratory environment. As shown in
explosion in test data imposes on test defects that percolated through the Figure 1, six test cells can fit within a
engineering is the ever-lengthening cyclization process, or they may have 5m by 5.5m laboratory space.
time required for test-pattern validation, resulted from the cyclization process
which is impacting time to market. Test- itself, or they may result from corner Bridging pre-silicon verification
pattern validation determines whether cases that the original design did not and post-silicon
the patterns are generated correctly, that take into account. Whatever the reason, An engineering lab with automated,
the expected responses are accurate, and the PSV process must identify them and parallel test stations can significantly
that they have enough margin to account correct any errors. enhance the test engineering process
for parameter variations (for example, in Correcting test-pattern errors. where the t y pical test content is
voltage and frequency) in production. When errors are detected during the dominated by structural test. However,
pattern validation process, they must wh i le t he s t r u c t u r a l t e s t i s t he
Generating test patterns be corrected through manual or a foundation for systematic test coverage
The test patterns include structural combination of manual and automated according to targeted fault models,
scan patterns generated by automatic methods. Engineers can manually there is a growing need for functional
test-pattern generators or functional rev iew t est pat t e r n s to ide nt if y tests to reach high-volume readiness.

28
28 Chip Scale Review July • August • 2023 [ChipScaleReview.com]