Page 13 - Chip Scale Review_March April_2023-digital

The distributed computing concept the use of hybrid bonding technology 9. Y. Kagawa, et al., “Novel stacked
for the new chiplet era is driven by for its product roadmaps for high-end CMOS image sensor with advanced
reduction of yield loss due to defect performance enhancements without Cu2Cu hybrid bonding,” IEEE
density. The same defect density the need to wait for the next advanced IEDM, Dec. 3-7, 2016.
cost drivers that moved the industry node transistor release. The ability to 10. P. Clark, “China’s YMTC takes lead
away from monolithic die to chiplets use advanced packaging technology in 3D-NAND memory,” EETimes,
is also important for hybrid bond to achieve the equivalent performance Technology News, April 13, 2020.
interconnect technology that requires a of an advanced node – in a shorter 11. J. A. Theil, et al., “Analysis of die
clean environment. This alignment of development time – has the chiplet edge bond pads in hybrid bonded
shrinking components for a distributed industry exhilarated about a ubiquitous multi-die stacks,” 72nd IEEE ECTC
architect u re is advantageous for heterogeneous integration supply (2022).
hybrid bond yield enhancements too. chain. While the future will unveil 12. G. Gao, et al., “Low-temperature
The combined enhancements of die the proliferation rate of this high- hybrid bonding for die to wafer
yield, electrical performance and performance interconnect through the stacking applications,” 71st IEEE
thermal performance is a compelling supply chain and market, it appears ECTC (2021).
argument to integrate the 3D chiplet this is only the beginning of a new 13. A. Agrawal, et. al., “Thermal and
with a hybrid bond interconnect. generation of packaging innovation electrical performance of direct
T he c o n s e r va t ive n a t u r e of t he with hybrid bonding. bond interconnect technology for
semiconductor industry demands that 2.5 and 3D integrated circuits,”
we invest in technologies that will References IEEE 67th ECTC, May 2017.
serve multi-generations of product 1. G l o ba l H i g h -P e r f o r m a nc e 14. K. Heyman, “DRAM thermal
enhancements that echoes the value of Computing (HPC) market size by issues reach crisis point,” June 9,
the scalable hybrid bond interconnect. component (solutions, services) 2022, Semiconductor Engineering.
L . C a o o f A S E e x p l a i n e d t h e Deployment type (on-Premise, 15. L. Cao, ”Advanced packaging
significant value advanced packaging Cloud); Report ID 6826. By server tech nolog y for chiplets and
brings to the semiconductor industry Price Band; Sept. 2022. heterogeneous integration,” Chiplet
by offer ing numerous options to 2. S. Naffziger, “Chiplet architecture Summit Conf., 2023.
achieve higher performance modules for high-performance server and 16. L. Su, Computex 2021, May
[15]. More importantly, the OSATs desktop products,” International 2021; https://www.youtube.com/
appear to be evaluating hybrid bonding Solid State Circuits Conf. (2020). watch?v=gqAYMx34euU
technology and the appropriate timing 3. L. Mirkarimi, A. Nuruzzaman, “A
to provide that service, which signifies new era of computing performance
t he ex p e c t at ion of h ig h -volu me with hybrid bonding,” Chip Scale
customer interest [15]. Review, July-Aug 2021.
4. “The Semiconductor and Packaging
Summary Report,” Prismark Partners, 2022.
AMD, an industry leader in 2.5D 5. CHIPS: https://www.darpa.mil/
chiplet architecture, released its 3D program/common-heterogeneous-
chiplet technology and first hybrid- integration-and-ip-reuse-strategies
bonded module for the Ryzen series 6. T. Hackenberg, “The chiplet
5900 [16]. The L3 cache is bonded to a market,” Chiplet Summit Conf.,
5000 series processor. The interconnect Jan. 2023 (San Jose, CA).
pitch of ~9μm is only achievable 7. P. Kennedy, “Intel enters a new
via a hybrid-bond interconnect and era of chiplets that will change
represents a 200x times the density of everything,” Serve the Home
2D chiplets. Similarly, other thermal Forum, Aug. 2022.
enhancing die were bonded in this 8. B. Baktha, “RISC-V and chiplets
module to obtain the 15% average powering the next leap forward in
performance improvement, which is compute systems architecture,”
equivalent to an advanced node. After Chiplet Summit, Jan. 2023 (San
this announcement, Intel discussed Jose, CA).

Biography
Laura Mirkarimi is SVP of Engineering at Adeia, Inc., San Jose, California. She earned a PhD in Materials
Science at Northwestern U. She leads the 3D Technology Team at Adeia and focuses on hybrid bonding,
advanced packaging and thermal management technologies for future generations of electronic products. Prior
to Adeia, she developed electronic devices including ferroelectric memory, transparent conductors and photonic
crystal sensors at Hewlett Packard Laboratories for 12 years. Email laura.mirkarimi@adeia.com

Chip Scale Review March • April • 2023 [ChipScaleReview.com] 11 11