Page 10 - Chip Scale Review_March April_2023-digital

that is designed to be combined with The value proposition of the new showed a major shift toward distributed
other chiplets to complete a fully- chiplet era is to fundamentally reduce computing [7]. Recently, Ventana
functional module within a package cost, while delivering enhanced features announced its partnership with Intel
or system. Chiplets require an I/ in electronic products. The main themes Foundries and shared a customer case
O controller die to bring the multi- for cost management are die size study where the development costs
chiplet module together to function shrink, disaggregation, reduced time to could be reduced by a factor of 8 by
as an IC. The advantages touted market, standardized I/O protocol, and using the distributed chiplet compute
over traditional SoC packaging are increased IP reuse. At the Intel- architecture [8]. Smaller chips have
heterogeneous integration, known good Architecture Day 2020, the vision of higher yield because of lower defect
die and reusable IP for a multitude creating multiple chiplet cores that density physics. Disaggregation is
of applications. connect to memory in the substrate important for the ability to use legacy
chips as appropriate, and optimally
process the various silicon circuit parts
within the supply chain. For example,
depending upon the specific application,
A/D converters are better with legacy
nodes, while some processors are better
suited at the latest node. Design and
fabrication of ICs in the most favorable
node or process offer more options for
cost savings. Reuse of chiplets reduces
the development time of product
families while delivering performance
differentiators to the market in a
timely fashion, thereby reducing
development costs.
It sou nd s l i ke a utopia for IC
architects. The packaging reaggregation
br ings the realit y of integ ration
challenges including lack of scaling
and performance with the conventional
Cu microbump and non-standard IP
among various packaging approaches
within the industry. Products today have
limited I/Os at 25μm pitch; however,
many chiplets and 2.5D modules would
benefit from finer pitch interconnection
between memory and logic or logic/
log ic i nter faces deliver i ng h ig h
bandwidth and low latency, all critical
for computation.

Hybrid bonding
The industry has been manufacturing
fine-pitch direct bond interconnect
®
(DBI ) hybrid bonding in wafer-to-
wafer applications such as image
sensors (~2.5-8μm) since 2016, and
more recently, NAND memory (~1μm)
because the manufacturing ecosystem
was ready [9,10]. Hybrid bonding
requires a level of cleanliness (i.e.,
ISO-5 to ISO-4) like back-end-of-line
(BEOL) wafer fabrication; therefore,
the wafer bonding process line had
an im mediate home. In cont rast,
die-to-wafer and die-to-die hybrid
bonding manufacturing readiness
have been in development for many
years. The advanced packaging OSAT

8 8 Chip Scale Review March • April • 2023 [ChipScaleReview.com]