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2019, pp. 1– 6, doi: 10.23919/
IWLPC.2019.8914120.
3. K. Ueno, K. Dohi, K. Muranaka, Y.
Ishikawa, A. Nakao, “Development
of liquid, granule and sheet type
epoxy molding compounds for fan-
out wafer-level package,” IEEE LEADERS IN
67th Elec. Comp. and Tech. Conf.
(ECTC), 2017, pp. 285–291, doi: MICRO DISPENSING
10.1109/ECTC.2017.264.
4. K. Ueno, K. Dohi, Y. Suzuki, M. TECHNOLOGY
Hirose, “Development of sheet
type molding compounds for panel-
level package,” IEEE 69th ECTC, SMALL REPEATABLE VOLUMES
2019, pp. 2162–2167, doi: 10.1109/ ARE A CHALLENGE, BUT NOT
ECTC.2019.00-23. IMPOSSIBLE IF YOU HAVE BEEN
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5. I . Wa t a n a b e , M . Kou d a , K .
Makihara, H. Shinozaki, “Latest
material technologies for fan-
out wafer-level package,” China
Semiconductor Tech. International TO DO IT WELL,
Conf. (CSTIC), 2017, pp. 1–3, doi: WE PROVIDE THREE THINGS:
10.1109/CSTIC.2017.7919860.
6. B. Julien, et al., “Development
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process for fan-out wafer-level Dispensing Expertise in a variety of microelectronic
packaging,” IEEE 70th ECTC, packaging applications.
2020, pp. 1965–1972, doi: 10.1109/
ECTC32862.2020.00306. Feasibility Testing & Process Verification based
7. Y. Kajikawa, “Fan-out wafer- on years of product engineering, material flow testing
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manufacturing solution for fan-
out WLP/PLP by DFD (die face Product Development for patented valves,
down) compression mold,” IWLPC, dispensing cartridges, needles, and accessories.
2020, pp. 1–8, doi: 10.23919/
IWLPC52010.2020.9375899.
8. T. Hasegawa, H. Abe, T. Ikeuchi,
“Wafer-level compression molding
compounds,” IEEE 62nd ECTC,
2012, pp. 1400–1405, doi: 10.1109/
ECTC.2012.624. Our Micro Dispensing product line is proven and trusted by
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Biographies
Nabankur Deb is a Pathfinding Packaging Engineer, in the Wafer Assembly Pathfinding Group, at Intel
Corporation, Hillsboro, OR USA. He completed his undergraduate studies at IIT Delhi and earned a PhD
from Georgia Tech in 2016. He then joined the lithography module at Intel Oregon as a Process Engineer. He
eventually joined the Pathfinding Group where he has worked on several first of a kind tool setups. He currently
has over 15 publications. Email nabankur.deb@intel.com

Xavier Brun leads the Wafer Assembly Pathfinding Group and Hybrid Bonding Prototyping at Intel
Corporation, Chandler, AZ USA. He joined Intel Arizona in 2008 as a Packaging Process Engineer after receiving his PhD from
Georgia Tech. In 2014, he moved to Oregon leading the pathfinding activities of several key initiatives (EMIB die preparation,
temporary carrier solution, and backside metallization). He currently holds 13 US Patents and 2 Intel Achievement Awards.

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