Page 67 - Chip Scale Review_November December_2021-digital

Digital twin construction requires components are typically designed overall design process while providing
tools that can aggregate data from by separate designers and teams who comprehensive design rule checking
different sources and in different formats may or may not communicate and (DRC), layout vs. schematic (LVS), and
into a cohesive system representation collaborate efficiently and consistently layout vs. layout (LVL) verification of
suitable to drive verification and with each other. When these designs are both the individual components and the
analysis, ideally using industry-standard integrated, a number of system-level final, assembled package.
formats. The tools should be able to verification and validation procedures Verification procedures must also be
automatically recognize device and are required to ensure that they are capable of managing the complexity and
substrate interfaces without having to connected correctly, both logically scale of such a fully-integrated 2.5D/3D
instantiate pseudo-components. This and physically. Ideally, the solution assembly, where die pins can equal/exceed
enables multi-designer asynchronous should be minimally disruptive to the 40,000 and total interposer pins can easily
design, allowing co-development by
different teams on different timelines in
different locations.
Designers must account for the Laser Assisted Bonding
manufacturing layer sets, position within
the package, and scale factor of each
component and die. At the same time,
they must manage and optimize the
connectivity throughout the hierarchical
multi-die, multi-substrate system. This
process includes defining and optimizing
the pin-outs required for package
substrates, silicon interposers, and new
ICs. Signal to pin assignments, as well as
power/ground patterns, must be defined.
O n c e a l l t h e c o m p o n e n t s a r e SMD LED
accurately captured, the next step • SMD placement on ultra-thin flex • Mini & Micro LED assembly for
is the construction and definition of repair and mass transfer
the reference top-level netlist of the
complete, integrated FOWLP. It is
critical to build this netlist correctly, as
it will be used to drive the verification
of the final assembled device at multiple
levels. The preservation and reuse of
original data, such as a device’s Verilog
description, is essential. The greatest risk
exists during translation or conversion,
such as with a schematic or spreadsheet.
If this step is done incorrectly, the VCSEL 2D - 2.5D Packaging
“digital thread” breaks and the threat of • diode assembly in between • Chip on wafer, chip on board, chip
connectivity errors rises steeply. cooling block on chip, package on package

Let’s get physical…and electrical
Because FOWLP manufacturing
technologies differ substantially from
traditional organic laminate substrate
packages, the verification process is
also substantially different. One major
difference is the use of GDSII instead of
Gerber as the manufacturing interface
format, and the challenges that brings to the 3.5D Multilayer Die Stacking 3D Packaging
design process. With such a very different
fabrication process comes a very different • Horizontal & vertical chip assembly • In-situ die placement & reflow
• No requirement for TSV structures
• Lowest thermal & mechanical stress
verification process that introduces • Simplification of complex package • High chip stack uniformity
unfamiliar verification rules, technologies, design
and associated methodologies.
FOWLP packages typically contain
multiple devices and multiple substrates www.pactech.de
that are often stacked (Figure 3). These sales@pactech.de

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