Page 69 - Chip Scale Review_November December_2021-digital

die systems) and die to controlled
collapse chip connection or ball grid
array (C4 or BGA) bumps (for both
single-die and multi-die systems) as
intended by the designer.
Regardless of the configuration, it all
starts with the ability to generate and
manage a system netlist. The system
netlist is compiled from the digital twin
of the overall assembly, as discussed
earlier. This system, or reference
netlist, is then compared against the
physical design connectivity derived
from the manufacturing data, such as
GDS. Warnings or violations can be
highlighted in the digital twin model to
trace and debug errors.
FOWLP connectivity verification
begins by separating process and
assembly integration rule requirements
from the design assembly definition.
The package house or OSAT company
is responsible for creating, validating,
qualifying, and delivering the package E-Tec Interconnect AG, Mr. Pablo Rodriguez, Lengnau Switzerland
and interface r ules. The package Phone : +41 32 654 15 50, E-mail: p.rodriguez@e-tec.com
designer is responsible for describing
how the assembly is put together, so the
tool can understand how to differentiate
the layers per die. This step can be
automated by extracting the assembly
design information from the design tools
used to build the flow.
Syntax in the verification tool can
combine the two types of rules and
provide rule checking capabilities. With
this information, the designers can
compare the physical package assembly
against a source netlist. Errors can be
highlighted in the package design as well
as in an extracted netlist representing
the assembly in order to cross-probe
connectivity results.

The essential kit
Another difference between traditional
printed circuit boards (PCBs) and
FOWLPs is the greater level of guidance
FOWLP designers require from the
manufacturer/fabricator. This need has
driven an entirely new approach for
sign-off quality physical verification of
packages: the ADK.
An ADK provides a standardized
process both chip design companies
and assembly houses can use to ensure
the manufacturability and performance
of FOWLP packages. Similar to an
IC process design kit (PDK), an ADK
includes the standardized rules, qualified
tool flows, interface formats, and input/

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