Page 36 - Chip Scale Review_November December_2021-digital

Apart from conventional transistor also improve the bandwidth and energy- each generation, severely restrict
and interconnect scaling, the massive efficiency of the entire chip. Various their use for future technology nodes.
computing requirements for future approaches such as through-silicon Monolithic-3D (M3D) integration
generations necessitate the need for via (TSV), flip-chip or wire bonding, is another type of 3D integration
alternative architectures. One such have been used for interconnecting scheme, where multiple stacked tiers
approach is 3D integration, or the multiple levels in a 3D-IC for a long are fabricated sequentially on the same
sequential stacking of chips—including time. However, their large parasitic wafer via deposition/recrystallization of
front-end-of-line (FEOL) and BEOL capacitances and severe electrical, the upper tiers (Figure 10b).
materials, devices, and interconnects t her mal, mecha n ical reliabilit y, Theoretical studies have demonstrated
in the vertical direction, which can not and adhesion challenges, as well as that graphene-based interconnects,
only reduce the interconnect delay, but increasing costs and complexity with inductors, and shielding layers in
conjunction with 2D semiconductor
material-based transistors can improve
the integration density by more than 10-
fold when compared to TSV-based 3D
integration density, and by more than
1.5-fold when compared to conventional
monol it h ic 3D i nt eg r at ion [19].
Additionally, the integration of logic and
memory levels (Figure 10b) using M3D
integration can alleviate the memory
wall problem for today’s computing
architecture, paving the way for high-
speed data transfer and computation.
Consider, for example, the recently
demonstrated 0.5T0.5R ultra-compact
hybrid memory cell that reduces the
device count by half for the very first
time in resistive random-access memory
(RRAM) technology history. It also
simultaneously allows for higher lateral
and vertical (3D) integration density
with respect to the conventional 1T1R
architecture, and can be monolithically
3D-stacked to build the ultimate high-
density nonvolatile memory arrays and
neuromorphic/in-memory computing
systems, with significantly higher
vertical density than the conventional
1T1R architecture (with RRAM on top
of the transistor). These attributes enable
unprecedented performance and energy-
efficiency to emulate the workings
of the human brain in the near future
[20]. Therefore, effective methods for
the seamless integration of graphene/
MLG, and/or other 2D materials with
mainst ream CMOS could lead to
revolutionary new devices, circuits,
and beyond-Moore architectures to fuel
next-generation electronics.
Summary
BEOL passive devices including
metal interconnects and inductors are
facing fundamental scaling limitations
that threaten to derail Moore’s Law.
Pioneering inventions led by Professor
Kaustav Banerjee at UC Santa Barbara
have revealed that judiciously engineered

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34 Chip Scale Review November • December • 2021 [ChipScaleReview.com]