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The visualization of the die placement
data using heat maps, histograms,
vector plots, etc., provides the process
engineer with the ability to optimize
and predict the impact of stepper field
size on production yield and throughput.
Moreover, this revolutionary capability
provides foresight, enabling the user
to quickly feed data to upstream and
downstream processes to prevent costly
rework and scrapped product. Future
software developments will provide
a method to dynamically balance
Figure 8: Predicted a) dX and b) dY overlay data histogram (mm) for 6x6 field size, where some die are out of throughput with yield.
specification, thereby reducing yield.
increase throughput, but reduces the ability and process development. For example, Acknowledgements
to correct for individual die placement polyimide processing is normally a non- This article is based on a paper
errors. By evaluating virtual exposures reworkable process step and overlay presented at the International Wafer Level
for different field sizes – and with each errors at this stage result in scrapped die. Packaging Conference (IWLPC) 2019.
exposure corrected to optimize yield Typically, if there is a die placement error The authors wish to thank Amr Hafez,
within the exposed field – it is possible to that exceeds the specification of the multi- Phil Convey and Karie Li for their work on
maximize process yield (defined as the die exposure field it will only be observed the software algorithm, which was key to
percentage of die that will meet the overlay after fully processing the polyimide delivering the die placement error solution,
specification) and quantitatively evaluate lithography and measuring overlay. By Burhan Ali for his support of the AOI
trade-offs between yield and throughput for this time, it would be too late to recover, system, and Corey Shay for his stepper
different field sizes. Only by having real- requiring the die to be scrapped. With support. Finally, we thank ESWIN, which
time data analysis can the user identify the the ability to pre-measure and predict the provided the dummy die panels necessary
correct settings and react to out-of-control yield with the AOI system and software for the yield prediction tests.
situations without impacting yield. algorithm, low yield could be avoided by
For the panels evaluated, the software reducing the field size. Moreover, the heat References
algorithm predicted 100% yield with map and histogram data could be sent 1. K. Best, M. Marshall, “Advanced
a field size of 3x3 (Figure 7). The dX “upstream” to the EMC process engineer packaging metrology and lithography
data was worse than the dY data, but all to address the root cause of molding that overcomes FOWLP/FOPLP die
die placements were within the +/-15µm process die placement error excursion. placement error,” IWLPC 2018.
via to pad overlay specification. As the 2. K. Ruhmer, “Lithography challenges
stepper field size was increased to 6x6 Summary for 2.5D interposer manufacturing,”
die, the yield drops to 99.42% as some of It is clear from the experimental data ECTC 2014, Orlando, FL, USA.
the die dX overlay errors exceeded the +/- that the calculated feed-forward site 3. R. McCleary, “Panel-level advanced
15µm specification (Figure 8). corrections provided the stepper with the packaging,” ECTC 2015, Las Vegas, NV.
The software algorithm’s yield ability to automatically compensate for 4. K. Ruhmer, P. Cochet, R. McCleary,
prediction has been compared to actual die placement error. This is a significant “Panel-based fan-out packaging to
customer product overlay measurements, improvement over the industry standard, reduce Costs,” SMTA/Chip Scale
confirming the accuracy of the prediction where steppers use a simple linear Review, IWLPC, San Jose, CA, Nov.
is within 0.2% of final overlay results. model approach. Application of the site 11-13, 2014.
This result provided the user with corrections, with larger field sizes during 5. K. Ruhmer, P. Cochet, R. McCleary,
confidence that AOI pre-measurement stepping, increased the lithography N. Chen, “High-resolution patterning
of panels with product die can be used throughput significantly from 3 x 3 to 6 technology to enable panel-based
to determine the optimum field size, x 6 with low impact on yield, 100% to advanced packaging,” IMAPS 2014,
throughput and yield prior to coating the 99.42% respectively. This will naturally San Diego, CA, Oct. 13-16, 2014.
panel with polyimide or photoresist. This deliver commensurate reductions in cost
has significant advantages in both cost of ownership.

Biography
Keith Best is Director of Applications Engineering for the lithography business unit at Onto
Innovation, Wilmington, MA. He has over 30 years of semiconductor processing experience
and has held a variety of Applications positions for both device manufacturing and capital
equipment companies. Keith received his BSc Honors degree in Materials Science from the U. of
Greenwich, UK. He holds 16 US patents in the areas of photolithography and process integration.
Email Keith.Best@ontoinnovation.com

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