Page 22 - ChipScale_Mar-Apr_2021-digital
P. 22

References                           10. Y. Lin, et al., “Multilayer RDL   out  embedded  bridge,”  Symp.
          1.  R. R. Tummala, “Moore’s Law for   inter poser for heterogeneous      by  Yole Développement a nd
            packaging to replace Moore’s Law    device and module integration,”    NCAP on Advanced  Packaging
            for ICs,” Chip Scale Review, vol.   2019 IEEE 69th ECTC, Las Vegas,    Semiconductors (SYNAPS), Wuxi,
            23, pp. 31-34, Jan-Feb 2019.        NV, USA, 2019, pp. 931-936, doi:   China, Sept. 15, 2020 (keynote,
          2. X. Zhang, et al., “Heterogeneous   10.1109/ECTC.2019.00145.           virtual).
            2.5D integration on through-     11. P. Yu, et al., “Coaxial through-  18. C. Key Chung, “Recent progress
            silicon interposer,” Appl. Phys.    silicon  vias  using  low-κ  SiO 2   of chiplets integrated packages
            Rev. 2., 021308 (2015).             insulator,” IEEE 70th ECTC,        in semiconductor industry,” 2020
          3. J. Lau, “Redistribution layers for   O r l a n d o , F L , U S A , 20 20 ,   SEMICON Taiwan, Heterogeneous
            heterogeneous integrations,” Chip   pp. 1167-1172, doi: 10.1109/       Integration Innovation Zone:
            Scale Review, vol. 23, pp. 20-25,   ECTC32862.2020.00187.              Fan-out Packaging Technology
            Jan-Feb 2019.                    12. J-K. Fang, M-L. Huang, H-J. Tu,   Seminar,  Taipei,  Sept  23,  2020
          4. J. Lau, “Recent advances and       W-L. Lu, P. Yang, “A Production-   (invited speech).
            trends in fan-out wafer/panel-level   worthy fan-out solution - ASE   19. J. Lin, C. Key Chung, C.F. Lin, A.
            packaging,” J. of Elec. Packaging,   FOCoS chip last,”  IEEE 70th      Liao, Y. J Lu, J. S. Chen, D. Ng.,
            vol. 141, pp. 1-27 (2019).          E C T C , O r l a n d o , F L , U S A ,   “Scalable chiplet package using
          5. F. S ho o , S . E l i s a b e t h , “ 3D   2020, pp. 290-295, doi: 10.1109/  fan-out embedded bridge,” IEEE
            p a ck a g i n g  i s  b r e a k i n g  n e w   ECTC32862.2020.00055.  70th ECTC, Orlando, FL, USA,
            ground,” Yole Développement      13. C. Key Chung, et al., “Alternative   May 26-29, 2020; pp. 14-18, doi:
            2020 (WebCast).                     solution for 2.5D package using    10.1109/ECTC32862.2020.00015
          6. C. Lee,  et al., “An over view     FO -MCM a nd FOEB,”  I EEE         (virtual).
            of the development of a GPU         22nd Elec. Packaging Tech. Conf.   20. R. Mahajan, et al., “Embedded
            with integrated HBM on silicon      (EPTC), Singapore, Dec 2-29 2020   multi-die interconnect bridge
            inter poser,”  2016 IEEE 66th       (Invited Talk, virtual).           ( E M I B)  - - A h i g h - d e n s i t y,
            Elec.  Comp.  and  Tech.  Conf.   14.  C. Key Chung, et al., “Silicon bridge   h i g h - ba n dw i d t h  p a c k a g i n g
            (ECTC), Las  Vegas,  NV,  2016,     using fan-out,” 2020 IEEE 14th     interconnect,” IEEE 66th ECTC,
            pp. 1439-1444, doi: 10.1109/        Inter. Microsystems, Packaging,    Las Vegas, NV, 2016, pp. 557-565,
            ECTC.2016.348.                      Assembly and Circuits Tech. Conf.   doi: 10.1109/ECTC.2016.201.
          7.  M. Koyanagi, “New 3D integration   (IMPACT-EMAP), Taipei, Taiwan;   21. R. Mahajan, et al., “Embedded
            t e c h n o l o g y a n d 3D s y s t e m   Oct 23-25, 2019 (invited speech).  multi-die interconnect bridge—
            LSIs,” 2009 Symp. on VLSI Tech.,   15. C. Key Chung, et al., “Advanced   A localized, high-density multi-
            Honolulu, HI, 2009, pp. 64-67.      packaging solutions for high-      chip packaging interconnect,”
          8. M. Chen, F. Chen, W. Chiou,        per for ma nce comput i ng a nd    IEEE Trans. on Comp., Packaging
            D .  C .  H .  Yu ,  “ S y s t e m  o n   big data processing,” IEEE 15th   and Mfg. Tech., vol. 9, no. 10, pp.
            Integrated Chips (SoIC™) for 3D     Inter. Microsystems, Packaging,    1952-1962, Oct. 2019, doi: 10.1109/
            heterogeneous integration,” 2019    Assembly and Circuits Tech. Conf.   TCPMT.2019.2942708.
            IEEE 69th ECTC, Las Vegas,          (IMPACT-EMAP), Taipei, Taiwan;   22. R. Viswanath, A. Chandrasekhar,
            NV, USA, 2019, pp. 594-599, doi:    Oct 21-23, 2020 (invited speech).  S. Srinivasan, Z. Qian, R. Mahajan,
            10.1109/ECTC.2019.00095.         16. C. Key Chung, Y. L. Huang,        “Heterogeneous SoC integration
          9.  A. Podpod, et al., “High-density   “ Ba c k - e n d b a s e d c h i p l e t   with EMIB,” 2018 IEEE Electrical
            and high-bandwidth chip-to-         integration solutions & roadmap,”   Design of Advanced Packaging
            chip  con nections  with  20μm      IEEE 40th Symposia on VLSI         and  Systems  Symp.  (EDAPS),
            pitch f lip-f lop  chip on  fan-out   Tech. and Circuits, Hawaii, USA.   Chandigarh, India, 2018, pp. 1-3,
            wafer-level package,” IEEE Inter.   Jun  15-19,  2020  (invited  short   doi: 10.1109/EDAPS.2018.8680869
            Wafer Level Packaging Conf.,        course, virtual).
            IW LPC 2018   doi: 10.23919/     17.  C . K e y C h u ng , “ L o w - c o s t
            IWLPC.2018.8573262.                 solution for 2.5D using fan-


                       Biographies
                         C. Key Chung is a Senior Director at Siliconware Precision Industries Co., Ltd., Corporate R&D, Taichung,
                       Taiwan, R.O.C. He received his PhD from National Taiwan U. and has 26 years experience in the industry
                       focused on packaging, substrate and assembly material. His team has won several advanced packaging
                       businesses including FO-PoP, FOMCM, FOEB, 2.5D, and 3DIC. He received 20 issued patents, published 45
                       papers, and delivered multiples invited talks at conferences. Email keychung@spil.com.tw

                         Shuai-Lin Liu is a Deputy Manager at Siliconware Precision Industries Co., Ltd., Corporate R&D, Taichung,
          Taiwan, R.O.C. He received his MS in Engineering Management from U. of Texas at Arlington, and has 10 years in the industry
          on material research and packaging.


        20
        20   Chip Scale Review   March  •  April  •  2021   [ChipScaleReview.com]
   17   18   19   20   21   22   23   24   25   26   27