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bonding, which involves selecting The so-called self-assembly technology a r c h i t e c t u r e s ,” 2 019 I E E E
high-topography tested chips (>2µm) relies upon the engineering of the surface 69TH Elec. Comp. and Tech.
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thanks to researchers’ deep expertise (in the three dimensions x, y, z) between core processor with 6 chiplets
in planarization. them. Figure 6 describes the concept in 3D-stacked on an active interposer
the case of two chips to be assembled. offering 0.6ns/mm latency, 3TBit/s/
2
Intel Components Research/CEA- This technology could offer an mm inter-chiplet interconnects and
Leti collaboration alternative to mechanical alignment 156mW/mm2@82% peak-efficiency
The semiconductor industry widely between the two areas, which could DC-DC converters,” 2020 IEEE
recognizes 3D integration technology be decisive in reaching high bonding Inter. Solid-State Circuits Conf.
and heterogeneous architecture as a throughput and ultimate accuracy as pick- (ISSCC), pp.: 46+ (DOI: 10.1109/
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Intel and CEA-Leti share the vision that leverage throughput, alignment accuracy, 6. A. Jouve, et al., “Die-to-wafer direct
advanced 3D integration and packaging and ultra-small dies bonding. hybrid bonding demonstration
tech nolog ies w ill st reng t hen I T with high alignment accuracy and
solutions, especially in the area of HPC. Summary electrical yields,” 2019 International
They signed an R&D agreement in 2016 The collaboration between CEA- 3D Systems Integration Conference
on several strategic research programs, Leti and Intel on silicon interconnect (3DIC), Sendai, Japan, October
including the Internet of Things (IoT), technologies between chiplet and active 8-10, 2019. Pages 1-7 (DOI: 10.1109/
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[8]. They extended this collaboration of the challenges involving material, (KGD) strategies compatible with
in 2020, where Intel’s Components processes and integration, and equipment. direct hybrid bonding,” 2020 IEEE
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working together on 3D heterogeneous concept released by CEA-Leti is very Three-Dimensional, Chiplet-Based,
technologies for HPC. encouraging. With Intel’s support and and Stacked ICs 3D&Chiplet Test,
T h e c ol l a b o r a t io n w i l l a l l ow the expected collaboration with different session 2.
both organizations to continue to players in the supply chain, particularly 8. https://www.leti-cea.com/cea-
investigate future opportunities for the equipment suppliers, this technology tech/leti/english/Pages/What’s-
heterogeneous integration roadmap may be a must-have technology for low- On/News/The-CEA-announces-
thanks to a combined broad base of cost, high-performance heterogeneous expanded-collaboration-with-Intel-
3D technologies involving both chip integration in the future. to-advance-cutting-edge-research-
packaging and interconnectivity. The and-innovation-in-key-digital-
work should ultimately pay off in References areas.aspx
solutions that offer flexibility in building 1. https://ieeexplore.ieee.org/stamp/ 9. A. Jouve, et al., “Self-assembly
large, high-performance, power-efficient stamp.jsp?arnumber=7545486 process for 3D die-to-wafer using
systems out of smaller functions. 2. ht t ps://newsroom.i ntel.com / direct bonding: a step forward
news/new-intel-architectures- toward process automation,“ 2019
Self-assembly technologies: the technologies-target-expanded- IEEE 69TH ECTC, pp.: 225-234
new deal market-opportunities/#gs.rp34uv (DOI: 10.1109/ECTC.2019.00041).
CEA-Leti published an approach at 3. https://newsroom.intel.com/news/
IEEE ECTC 2019 [9] that combines intel-unveils-new-tools-advanced-
advantages of die-to-wafer hybrid chip-packaging-toolbox/#gs.qov5x0
bonding and high throughput in the 4. P. Coud r ai n, et al., “Act ive
pursuit of anticipating coming challenges. interposer technology for chiplet-
b a s e d a d v a n c e d 3D s y s t e m

Biographies
Séverine Chéramy is Director of the Institute of Technological Research (ITR) 3D program and is also responsible
for 3DIC integration strategy and business development at CEA-Leti, Grenoble, France. She joined CEA-Leti in 2008
as 3D Project Leader, and was promoted in 2012 to 3D Integration Laboratory Manager. She holds an Engineering
Degree in Materials Science. Email Vincent Barral, Business Development Manager at vincent.barral@cea.fr

Johanna M. Swan is an Intel Fellow and the Director of Package Research and Systems Solutions in Components
Research within Technology Development at Intel Corporation, Chandler, Arizona, USA. She leads an
interdisciplinary team of researchers charged with developing novel technologies and package architectures to enable continued
semiconductor scaling such as the recent Omni-Directional Interconnect for 3D IC interconnects. Email johanna.m.swan@intel.com

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14 Chip Scale Review March • April • 2021 [ChipScaleReview.com]