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Figure 2: Intel’s packaging technology roadmap. © Intel
envisioned that the combination of EMIB for even higher performance. For chiplets and denser interconnects bring
with Foveros, or co-EMIB, will enable example, ODI allows top-side chiplets about new demands for assembly of the
increased partitioning opportunities by to take advantage of 3D stacking’s 3D stacks and may challenge traditional
interconnecting larger than reticle-sized high bandwidth while maintaining the methods. A key area of focus is a shift
base die and their respective stacked-die benefits of direct power delivery from the from a solder-based interconnect to hybrid
complexes (Figure 2). package, thereby avoiding losses that can bonding, which Intel discussed briefly
A s a n e x t s t e p i n o p t i m i z i n g accompany TSVs. at SEMICON West in 2019 and plans
perfor mance, Intel’s Components Bey on d t h e s e a r c h i t e c t u r a l to publish more about at ECTC in 2021.
Research introduced the omni-directional developments, Intel researchers are also Another vital area undergoing research is
interconnect (ODI) at SEMICON West working to scale the vertical interconnect enabling high-volume throughput in the
in 2019 [3]. This new building block is pitch between die. The shrinking of the assembly of these small chiplets to ensure
complementary to EMIB and Foveros pitch enables much higher interconnect handling and high yield. In this regard,
because it offers additional degrees of density or die size area reduction, or a Intel is researching forward-looking
freedom for interconnecting die together combination of both. The ever-smaller methods such as self-assembly of chiplets
into multi-die complexes (Figure 3).

CEA-Leti’s heterogeneous silicon
technology strategies
HPC systems development must
take full advantage of 3D integration
technologies to overcome bandwidth
limitations between memory and CPU
while improving performance for each.
As the reduction of 3D interconnect pitch
improves data bandwidth (Gb/s/mm²) for
memory-bound applications, advanced
assembly technologies leverage tight
heterogeneous integration with a low
energy profile (pJ/b), which is useful for
compute-bound applications.
Pursuing this objective, CEA-Leti
introduced IntAct in 2019 at IEEE ECTC
[4], a proof-of-concept demonstration
integrating a 96-core architecture
Figure 3: Interconnect technologies versus required pitch. © Intel comprising six chiplets (fully-depleted

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