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whereby the ICP etching sputters some
of M1 because of the low dielectric
selectivity. This sputtered metal changes
the TSV-to-M1 contact resistance. From
this data it is clear that Bosch etching
of nano-TSVs appears more stable and
reliable than ICP etching.

Summary
Sub-500nm pitch interconnects that
electrically connect the back side and
front side of a device wafer have been
realized by combining extreme wafer
thinning to 500nm and nano-scale
via-last formation. A combination of
grinding, CMP, dry etching and wet
etching can be used for the thinning of
wafers so long as they contain a grown-
in SiGe etch stop layer. Tight control over
the final Si thickness has been achieved
with TTV <70nm. Nano-TSVs with
180nm minimum CD have been etched
through the remaining Si using a Bosch
process that has the required selectivity to
the M1 dielectric and the desired sidewall
quality for subsequent deposition and
plating. Functional electrical structures
have shown 99% yield of the front-side
to back-side connections and the data
confirms the overlay between front side
and back side to be <15nm.

References
1. J. De Vos, et al., “Hole-in-one TSV, a
new via-last concept for high-density
3DSOC interconnects,” ECTC, 2018.
2. A.Jourdain, et al., “Extreme thinning
of Si wafers for via-last and multi-
P 3. A.Jourdain, et al., “Extreme wafer
wafer stacking applications,” IEEE
RoHS
ECTC, May 2018.
thinning and nano-TSV processing
for 3D heterogeneous integration,” in
IEEE ECTC, June 2020.
4. S. Van Huylenbroeck, et al., “A
highly reliable 1x5μm via-last TSV
module,” IITC, 2018.

Biographies
Dave Thomas is VP, Product Management at SPTS Technologies, Newport, UK. With previous positions at
Philips Components and Nortel, he has been with SPTS since 1994, working with both PVD and Etch product
lines. He holds a BSc in Chemistry from Leeds U. (UK), and an MSc in Surface Chemistry and PhD Plasma
Etching & Deposition from U. of Bristol (UK). Email Dave.Thomas@spts.com
Anne Jourdain is a Principal Member of Technical Staff at imec, Leuven, Belgium. She joined imec in 1999,
and is currently responsible for process integration activities and wafer thinning in various projects within the
imec’s 3D System Integration Program. She’s also part of their STCO (System-Technology Co-Integration)
program. She holds an MSc degree in Opto-Microelectronics from Ecole Nationale Supérieure d’Ingénieurs de Caen (France)
and a PhD from U. Joseph Fourier of Grenoble (France).

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