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circuit boards (PCBs) and associated large number of superconducting chips. system integration for next-generation
assembly processing. In this approach, In Figures 5d and e, we also show a superconducting VLSI systems.
the superconducting test chip joined using schematic view of how these wafer-scale
niobium-indium or indium µ-bumps S-MCM signals will be routed through a Acknowledgments
that provide both electrical connectivity high-density interposer to produce wafer- We gratefully acknowledge M.A.
and mechanical stability between the interposer-wafer (WIW) configurations. Gouker, S.K. Tolpygo, R. Lambert, R.
different chips. The combination of I-line In general, three types of signals are D’Onofrio, C. Stark, and P. Murphy for
and LDW reduces the total number of envisioned: DC, 50 Ohm characteristic useful discussions, and K. Magoon, P.
masks. The use of single photoresist impedance for clock line, and 10-20 Ohm Baldo, T. Weir, M. Townsend, M. Augeri,
for UBM and micro-bump fabrication characteristic impedance for the data line. J. Liddell, B. Osadchy, M. Hellstrom, C.
not only reduces additional processing As we look further out, we also consider a Thoummaraj, and J. Wilson for valuable
steps, but also minimize/eliminate bump- superconducting PCB to assemble a WIW technical assistance. This research
related defects suitable for wafer-scale structure for various superconducting was funded by the Defense Advanced
S-MCM fabrication. Furthermore, LDW cryogenic packaging solutions. Research Projects Agency (DARPA).
lithography utilizes full-wafer real estate Opinions, interpretations, conclusions
and provides fan-out circuits for attaching Summary and recommendations are those of the
connectors and cables to connect with the The demand for superconducting authors and are not necessarily endorsed
next level of semiconducting electronics. computing scalability beyond arrays of by the United States Government.
Wafer-scale S-MCM circuits will a create a few superconducting chips is driving
a loss-less, superconducting path for chip- the need for greater wiring densities and References
to-chip communication, whereas the more functionality onto a single cryogenic 1. D. S. Holmes, A. L. Ripple, M.
traditional approach will go through a package. One way to address this demand M. Manheimer, “Energy efficient
multilevel of assemblies with many normal is with the use of flip-chip integration of superconducting computing-power
metal interrupted superconducting paths. wafer-scale S-MCMs with microbump- budgets and requirements,” IEEE
The niobium-indium microbump based interconnects to electrically Trans. on Applied Superconductivity,
thermocompression bonding approach interface multiple superconducting 23(3)1701610 (2013).
can be extended to attach multiple chips. Niobium-indium microbump- 2. R. N. Das, V. Bolkhovsky, S. K.
20mm x 20mm chips to a single, large based flip-chip interconnects are capable Tolpygo, P. Gouker, L. M. Johnson,
superconducting MCM wafer, which of maintaining very low interconnect E. A. Dauler, M. A. Gou ker,
is a valuable capability as we consider resistance, which are advantageous for “Large-scale cryogenic integration
scaling to larger systems, such as wafer- superconducting packaging. approach for superconducting high-
scale S-MCM demonstrations. The We have demonstrated large S-MCM performance computing,” IEEE
use of wafer-scale S-MCM technology (48 x 48mm ) fabrication with single I-line Electronic Comp. & Tech. Conf.
2
for the base superconducting module mask exposure and thermocompression (ECTC) Proc., 675-683 (2017).
enables a combination of active and bonding to attach up to 20mm x 20mm 3. R. N. Das, V. Bolkhovsky, C.
passive interconnect-based circuits; superconducting chips to the S-MCM Galbraith, D. Oates, J. J. Plant, R. D.
such an S-MCM could be used both module. We have shown that the sequential Lambert, et al.,“Interconnect scheme
for superconducting chips (single- exposure of two photomasks (e.g., A and B,) for die-to-die and die-to-wafer-level
f lux-quantum [SFQ], rapid single- with small overlap (stitched) can produce heterogeneous integration for high-
flux-quantum [RSFQ], quantum flux larger S-MCM substrates up to 96 x 96mm performance computing,” IEEE
2
parametron [QFP]) in proximity to with four masks/layer combined. I-line ECTC Proc., 1611-1621 (2019).
one another, along with auxiliary and laser direct write photolithography 4. R.N. Das, F. D. Egitto, J. Lauffer, B.
semiconductor electronics (e.g., power combinations demonstrated full-wafer Bonitz, B. Wilson, M. D. Poliks, et
supplies, clock generators, output S-MCM fabrication capability. These al., “3D-interconnect approach for
amplifiers) in a single system. combined features show the potential high end electronics,” IEEE ECTC
As illustrated in Figure 5, the multiple to scale S-MCM technology with high- Proc., 1333-1339 (2012).
wafer-to-wafer assembly approach density, low-resistance interconnects to
creates a system that can accommodate a wafer-size substrates, thereby enabling

Biographies
Rabindra N. Das is a Member of the Technical Staff in the Quantum Information and Integrated Nanosystems
Group, MIT Lincoln Laboratory, Lexington, MA USA. Prior to MIT, he was a Principal Engineer at Endicott
Interconnect Technologies (formerly IBM Endicott). Dr. Das has 18 years of experience in microelectronics
packaging development for applications ranging from HPC to medical to quantum electronics. He holds 48
patents and more than 100 publications. Email Rabindra.Das@ll.mit.edu
Vladimir Bolkhovsky is a Member of the Technical Staff in the Quantum Information and Integrated
Nanosystems Group, MIT Lincoln Laboratory, Lexington, MA USA. He has more than 40 years of experience
in the semiconductor industry and in superconductor process development. He received an MS in Chemical Engineering and
holds multiple patents and has more than 20 publications.

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