Page 20 - ChipScale_Jan-Feb_2021-digital

Wafer-scale superconducting multi-chip module

By Rabindra N. Das, Vladimir Bolkhovsky, Alex Wynn, Ravi Rastogi, Scott Zarr, Leonard M. Johnson
[Quantum Information and Integrated Nanosystems Group, MIT Lincoln Laboratory]
T his paper describes a strategy functionalities required for superconducting stitching) was evaluated. The S-MCM

to combine laser direct write
(LDW) and optical lithography computing architectures. However, such comprised four superconducting metal
(Nb) layers and one resistor layer, allowing
VLSI capability has yet to be demonstrated.
(I-line) to fabricate 200mm wafer-scale This paper presents a system-on-wafer for several impedance-controlled clock
superconducting multi-chip modules approach for integrating a large number and data lines. The MCM stack-up [2]
(S-MCM) for interconnecting multiple of SFQ chips onto a full 200mm wafer requires a 0.8µm wide line to achieve
active superconducting flux quantum S-MCM. This approach increases the 50 Ohms impedance. For S-MCM, all
(SFQ) chips for next-generation cryogenic circuit complexity (number of JJs) that can the critical layers with tight impedance-
processing systems. The packaging be integrated within a given cryogenic controlled lines are fabricated by I-line
strategy includes the development of space by producing high chip-to-chip lithography. The primary goal of this
S-MCM (48mm X 48mm) using large connectivity. Connecting superconductor design is to evaluate minimum feature
single I-line reticles, followed by reticle electronics components using our approach sizes for 48mm x 48mm circuits with a
stitching to fabricate nearly the largest enables a parallel scaling path. Connectivity single mask exposure. The design includes
possible stitched S-MCM (96mm X of individual chips through superconducting snake/comb test structures and critical
96mm) using a four mask/layer process. wiring offers significant advantages relative dimension (CD) cells (0.8μm lines) around
The stitching process starts with sequential to the equivalent integration methods for the 48mm x 48mm periphery to evaluate
exposure of multiple I-line photomasks semiconductor-based electronics. With the maximum S-MCM size within the
– with small overlap (stitched area) – low-loss superconducting lines, power limitations of the I-line photolithography
to realize larger combined circuit areas requirements for drivers and receivers tool; patterning aberrations may occur near
for design-critical S-MCM layers with for inter-chip communication can be the edge of the full reticle field, which is
minimum linewidths of 0.8-1μm. The equivalent to on-chip communication. monitored using these structures. Second,
process also utilizes laser direct write This kind of communication is in stark the design includes perimeter and interior
(LDW) lithography to make wider (>1µm) contrast to CMOS-based integration where array interconnects that cover full reticle
features such as fan-out circuits, extending the number of I/Os can quickly dominate (20mm x 20mm) to be tested with SFQ
the stitched circuit area to include the the power budget for a similar system. chip flip-chip bonding. Scanning electron
entire 200mm wafer as a single S-MCM. We present a niobium-indium microbump microscopy (SEM) results indicate that it
scheme to produce a variety of stitched is possible to create 48mm x 48mm critical
Introduction and wafer-scale S-MCMs. This scheme circuits with a single I-line mask exposure,
As CMOS reaches the end of Moore’s enables the heterogeneous integration with the potential to be extended to the
Law, scaling and power consumption of known good chips to increase circuit entire I-line field for stitched MCMs. In
continue to be a challenge, thereby driving density, functionality, and reduce the the next section, we will show stitching of
the need to develop “beyond-CMOS” circuit footprint. In addition, we discuss 48mm x 48mm I-line masks (four masks/
device technologies to advance high- thermocompression bonding of niobium- layer) to produce 96mm x 96mm MCMs
performance computing. Superconducting indium microbumps and their electrical with 0.8μm CDs for Nb routing layers.
electronics using Josephson junctions (JJs) performance at cryogenic temperatures. Prior to the stitching demonstrations,
as active devices are a promising candidate Development of wafer-scale S-MCM the flip-chip bonding process was tested
for high-performance computing because of proceeded in three steps. In subsequent using a two-component daisy chain
their extremely low gate energies, fast clock sections, we will discuss the fabrication of structure. The first half of the structure
speeds, and lossless signal propagation a single reticle S-MCM, multiple reticles consists of a single 200mm diameter
for data transport [1]. A major technical based stitched S-MCM, and stitched S-MCM with many 20mm x 20mm
challenge facing superconducting circuit reticles with laser direct writing based bumped areas. Each bumped area
technology is achieving a very large scale wafer-scale S-MCM. contains many short and discontinuous
of integration (VLSI). Developing a VLSI wire segments terminated at a bump
7
capability (10 or more JJs) with 100s of Single reticle superconducting on either end of the segment. The
SFQ chips in proximity to one another along MCM second half of the structure is created
with auxiliary semiconductor electronics As an intermediate step towards by passive 20mm x 20mm Si chips that
(e.g., power supplies, clock generators, demonstrating a large-area stitched contain complementary wire segments
output amplifiers) in a single system is S-MCM, a 48 x 48mm S-MCM fabrication terminated at bump pads; when the two
2
highly desirable to realize lossless circuit using a single I-line mask set (without halves are bonded together, they form a

18
18 Chip Scale Review January • February • 2021 [ChipScaleReview.com]