Page 16 - ChipScale_Jan-Feb_2021-digital

Figure 5: X-axis and Y-axis placement accuracy data at 16Kcph shows a standard deviation of <2.3µm.
of these heterogeneous integration
structures in a FOWLP, FOPLP, SLP
or embedded process requires that this
accuracy must be maintained over a
placement area as large as 600mm x
600mm (Figure 4). To determine the
feasability for these requirements,
we assembled over 12 panels with an
approximate 6mm x 6mm die with
sub-50µm pitch copper pillar bumps
utilizing our FuzionSC™ platform.
Four panels were built to establish
a baseline and to validate trimming
requ i rement s by spi nd le a nd by
placement location. These results were
Figure 6: Theta accuracy statistics for 40mm x 40mm die on interposer.
then incorporated into the placement
map of the system. Six panels were
then assembled and all placements were
measured for X, Y and Theta variation
(Figure 5). As can be seen from the
data, the system was validated to be able
to place die at speeds >16Kcph, with an
accuracy of <2.3µm standard deviations.
As die sizes for high-performance
computing applications grow, the theta
accuracy also becomes critical for
precision pad to bump alignment. A
study was completed assembling 40 large
bumped die on an interposer, with all
results measured (Figure 6). The results
of this study demonstrated a capability of
<0.075deg @ Cpk 1.56.
In high-volume manufacturing, active
monitoring and control is required
to maintain accuracy as a function
of temperature, time, or number of
placements, which prevent drift.
An example solution is an accuracy
management system (AMS), which
monitors the placement performance
of each spindle using a standard high-
Figure 7: XY scatterplot of AMS results. The table shows specification limits corresponding to Cpk values of 1.33 and precision slug, and actively adjusts
1.67 based on the above means and standard deviations. Data indicates system accuracies of <3.2µm @ Cpk 1.33.

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14 Chip Scale Review January • February • 2021 [ChipScaleReview.com]