Page 14 - ChipScale_Jan-Feb_2021-digital

Emerging process and assembly challenges in

electronics manufacturing

By Glenn Farris [Universal Instruments]
T he s e m i c o n d u c t o r a n d (AiP), microelectromechanical systems carrier is then reconstituted by molding,

semiconductor equipment
industries expect to see a (MEMS), high-performance computing followed by making a RDL atop the
( H PC), and advanced packagi ng
entire molded area (both atop the chip
strong upturn in the next few years, products, each of which benefit from and atop the adjacent fan-out area), and
with advanced packaging technologies this technology. These architectures then forming solder balls on top.
a significant beneficiary of the market’s also create several challenges for InFO (integrated fan-out wafer-
strength. 5G, artificial intelligence, edge efficient, cost-effective assembly. level packaging). InFO is an innovative
computing, persistent memory, integrated Accurate die placement, efficient wafer-level system integration technology
power management, and the transition changeover from picking one die type, platform, featuring high-density RDL
to sub-5nm silicon technology are all or wafer type, to a different type, and and through-InFO via (TIV) for high-
driving the need for innovative packaging the ability to mix wafer, tape, and tray density interconnect and performance
solutions. These solutions integrate fed material are critical to enable mass for various applications, such as mobile,
silicon produced with disparate process production solutions. high-performance computing, etc.
®
nodes and deliver maximum performance C oWo S (c h i p - on - w a f e r - on -
®
at optimal cost. Alternatives for implementing substrate). CoWoS is a 2.5D wafer-
Heterogeneous integration (Figure multi-die architectures level multi-chip packaging technology
1), which utilizes a multit ude of Multiple alternatives have been that incorporates multiple dies side-
interconnect methodologies (from fan- proposed to implement the multi-die by-side on a silicon interposer in order
architectures noted above. Some of these to achieve better interconnect density
examples are described below. and performance. Individual chips are
EM I B . E m b e d d e d mu l t i- d i e bonded through micro-bumps on a silicon
interconnect bridge (EMIB) is an elegant interposer forming a chip-on-wafer (CoW).
and cost-effective approach to the in- The CoW is then subsequently thinned
package high-density interconnect of such that the through-silicon via (TSV)
heterogeneous chips. EMIB uses a very perforations are exposed. This is followed
small bridge die with multiple routing by C4 bumps formation and singulation.
®
layers. This bridge die is embedded as A CoWoS package is completed through
part of the substrate fabrication process. bonding to a package substrate.
F O PLP (f a n - o u t p a n el - l e vel SOIC (small outline integrated
packaging). One of the latest packaging circuit). SOIC is a surface-mounted
trends in microelectronics is FOPLP, integrated circuit (IC) package that
which has a high potential for significant occupies an area about 30–50% less than
package miniaturization concerning an equivalent dual in-line package (DIP),
package volume, but also with respect with a typical thickness being 70% less.
Figure 1: Example of heterogeneous integration to its thickness. The technological SiWLP (system in wafer-level
application. core of FOPLP is the formation of a package). A SiWLP is fabricated using
reconfigured molded wafer combined “RDL-first” technology for FOWLPs and
out to silicon interposer, to chiplet), with a thin-film redistribution layer provides high chip-I/O density, design
addresses this challenge but requires (RDL) to yield a surface-mount device flexibility, and package miniaturization.
unique solutions for efficient, cost- (SMD)- compatible package. 2.5D. 2.5D is a packaging methodology
effective die placement. High-speed, FOW LP (fan - out wafer- level for including multiple die inside the same
high precision multi-die placement, packaging). FOWLP is an integrated package.
directly and efficiently extracted from a circuit packaging technology, and an eWFO (embedded wafer fan-out).
range of different sized wafers, is critical enhancement of standard wafer-level eWFO is fabricated in either wafer fabs
to enable cost-effective assembly. packaging (WLP) solutions. In FOWLP, using back end of line (BEOL) tools,
Complex multi-die architectures the wafer is diced first, but then the materials and processes, or at outsourced
support a wide range of applications, dies are very precisely re-positioned semiconductor assembly and test
including: insulated-gate bipolar on a carrier wafer or panel, with space suppliers (OSATS) using their built-up
transistor (IGBT), antennae-in-package for fan-out kept around each die. The fabs and tools.

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