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TECHNOLOGY TRENDS

Heterogeneous integration prompts test

content to “shift left”

By Dave Armstrong [Advantest America, Inc.]
H eterogeneous integration and and a wafer prober find hard rejects and people suggest that we are moving past the

the resulting need for known-
perform scan and some functional test at
parts per million into an industry where
good die (KGD) are driving
As a result of the new qualit y
the transition to a new test one temperature. At the KGD test step, parts per billion is the new norm.
automatic test equipment (ATE) and a
flow, best described as “shift left.” With singulated die prober confirm scan and requirements noted above, you have to do
this flow, test functions once performed at functional tests at a second temperature. At a lot more testing at wafer, or perhaps after
system-level test are moving to final test, or final test, ATE and a device/die handler with thin bump sawing, where you can actually
a KGD test step that occurs after thin-bump active thermal control perform packaged perform active-thermal-control thermal
sawing. Similarly, final-test functions are device test, extended scan test, parametric testing, where you can do full-power testing
shifting left to the KGD step or to the wafer- performance test, at-speed test, high- of your part, and where you can do at-speed
probing step (Figure 1). power test, and stress tests. And finally, a testing of your part. People are finding that
The need for this shift-left flow arises system-level tester repeats packaged device by being able to do at-speed, at-power test of
because many companies today are tests and performs boot-up tests and fuse KGD, they can do pretty much all the testing
starting to ship KGD—including some blowing. that they used to do at final test. In turn,
very complex artificial intelligence (AI) The flow described above may have been final test is becoming more of a system-
devices— and others are shipping memory sufficient five or six years ago when multi- level test step—performing boot-up testing,
stacks. In these examples, there is no longer die integrations might have had one large for example, and checking whether your
a packaged-device ship location. Shipping logic part and four high-bandwidth memory software and firmware are working.
parts in die form represents a new ship (HBM) devices. But today, people are A big challenge for heterogeneous
location, and you have a critical need for moving to heterogeneous devices that have integration is simple continuity. You might
more test content prior to that ship location 30, 40, or 50 devices on them, and the error have 40,000 bumps on your logic part, and
to make sure the devices are of sufficient elements of each one of those die multiply you may have ten of those logic parts, so you
quality for subsequent heterogeneous together. If you have 0.99% good devices easily could have a half a million bumps that
integration. Indeed, you may not have a and you multiply all the error elements have to make good contact. And then you
profitable product if you do not push your together, you could very easily end up with have other parts with other I/O, so you have
quality upstream. Pushing quality upstream an assembly that has only a 60% probability a very large amount of continuity checks
gets you profit downstream. of being good. So the fundamental challenge and interface tests to perform. And that’s
Consider the traditional test flow. At the is that you need to get not just 0.99% good where some of the IEEE standards come
wafer-test step, automatic test equipment parts, but 0.9999% good parts. This is where into play, because you can’t necessarily

Figure 1: Test content is shifting left, from system-level test to final test and KGD test—and from final test to KGD test and wafer-level test.

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