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apply as for the smaller consider a multi-chip module that, without
part. Consider single-site left shift, requires a 520s final test for
testing of a 10nm device 72.8% yield and a 1,040s system-level test
with 85 die per wafer. for 85.4% yield. The shift left flow reduces
Assume that without manufacturing cost 28% and increases parts
using a shift-left flow, shipped by 37% (Figure 5).
this device requires a
30s wafer-probe time Test system changes
at 75% yield and a 60s For an effective shift-left strategy,
KGD test time for 87.5% test systems will require some changes.
yield. With the shift- One key point is that active thermal
left flow, manufacturing control is becoming important, and it
cost increases 16%, is something you cannot do on wafer
but unfound failures probers. With wafer probers’ chucks and
Figure 2: This graph shows yield per step vs. test time per step for succes- shipped are reduced by high thermal mass, you can just set them
sive test steps; half the remaining faults were detected in the next step, which 53% (Figure 4). Finally, at a temperature and hope it stays there.
takes twice as long as the previous step.
check those externally. Consequently, IEEE
P1500 and related I/O tests are critical.
There are some misperceptions in the
industry that need to be addressed. For
example, you may ask, “If I get 90% yield,
have I got a 90% good product?” The
answer is no. You only know that 90% of
the tests you have run yield positively, but
the tests you have run may not cover 90%
of the potential faults. And then the next
question is, “If I spent ten seconds to get to
90%, how long do I need to spend to get the
rest of the percentage?” And here you face
the law of diminishing returns. You can
approach 100% coverage exponentially, but
some faults you are never going to find.

Math examples
Consider the math behind a sequence of Figure 3: For a small device, the shift-left strategy increases manufacturing cost by 9%, but reduces unfound
KGD test steps, based on some reasonable failures shipped by 51%.
assumptions regarding test time and quality
of product. Assume half of remaining faults
are detected in each successive test step,
which takes twice as long as the preceding
step (Figure 2). Further, assume a small
10x10mm device fabricated in 10nm
technology with 650 die per wafer and a
four-site test with 90% yield at wafer probe.
As shown in Figure 3, the shift-left strategy
increases manufacturing cost by 9% but
reduces unfound failures shipped by 51%.
The walkaway here is that you can increase
quality by finding 51% of the previously
unfound faults before shipment with a small
investment in additional testing.
For a larger logic part, you will have to
work harder to obtain observability and
controllability, and test time will be longer.
Nevertheless, the same metric seems to Figure 4: For a large logic part shipping as a KGD using the shift-left strategy, manufacturing cost increases
16%, but unfound failures shipped are reduced by 53%.

8 8 Chip Scale Review January • February • 2021 [ChipScaleReview.com]