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September • October; Volume 23, Number 5

Cover Photo

An illustration of the latest development towards the integration of ultra-thin silicon bare dies within a flexible film. ChipInFlex is a generic wafer-level process for manufacturing a flexible label that integrates silicon components. Working on a silicon carrier helps achieve a high resolution of integration. The process described is the first to offer flipchip silicon dies interconnection within a flexible film and collective thinning.


Photo courtesy of CEA-Leti

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White Paper: System-level, post-layout electrical analysis for high-density advanced packaging
As HDAP designs become more popular, the need for post-layout simulation (analog) and post-layout STA (digital) flows to augment basic physical verification (DRC and LVS) is growing. Mentor provides an accurate, automated flow that generates the required HDAP netlist for simulation/STA to enable HDAP designers to ensure that the HDAP will perform as designed.
Mentor, a Siemens Business

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