March • April 2018; Volume 22, Number 2
The photo is a graphical representation of an intermediate step in the RDL-first fan-out process whereby the dies are placed on top of the redistribution layer (RDL) architecture before overmolding. Prior steps in the process include application of a release layer to the carrier, followed by addition of redistribution layers on top of the release layer. The RDL-first fan-out process offers distinctive advantages in terms of reduced known good die (KGD) loss, improved line/space density, etc.
Cover photo courtesy of Brewer Science Inc.
Read the issue
Download PDF Subscribe
With extensive product and process development expertise, customers can utilize Bourns for:
We help fabless IC companies miniaturize and productize their chip-level designs into MMICs, CMOS, SiGe, GaAs, InP, GaN or SiC Multiple-Chip Modules, 100-400Gbps Optoelectronic Packages or RF/Microwave Board Assemblies.
San Jose, California – USA –
The IWLPC Technical Committee is pleased to announce the Best of Conference, Best Presentation & Best Papers in WLP, 3D, Advanced Manufacturing and Test tracks as chosen by the technical committee and attendees based on technical merit, relevance, originality, knowledge of subject, quality of material, and quality of presentation.
GRENOBLE, France – Nov. 28, 2017 – Leti,
a technology research institute of CEA Tech, today announced that Emmanuel Sabonnadiere has been named CEO, succeeding Marie-Noelle Semeria.
Sabonnadiere, who has more than 25 years of executive leadership experience in a variety of large technology environments, joins Leti from CEA Tech, where he led the industrial-partnership program. He brings a strong background in new-technology development with broad private-sector expertise in operational excellence, team building and guiding multicultural organizations in business transformation in Europe and globally.
As in prior years, the in-depth presentations at this year's IWLPC, covering a broad array of the industry's critical challenges, did not disappoint. A series of keynote presentations and papers included a couple of major announcements that will be discussed below. Of special note, several keynote speakers focused on heterogeneous integration and the added complexities of migration to large rectangular panels. The session presentations reported impressive progress in material science, manufacturing processes, new equipment, metrology, and testing. A few selected highlights, only limited by the allotted space, are included below.
Wednesday, April 18, 2018 - SEMI Global Headquarters - Milpitas, CA
Emerging ADAS Thermal Performance and Reliability: Needs and Solutions Karthik Srinivasan, Senior Corporate AE Manager, Analog & Mixed Signal Products, Semiconductor Business Unit, Ansys Inc. ...>>
April 26, 2018 – NextFlex Facility - San Jose, CA -
Unlike computers and mobile phones, the Internet of Things demands a wide range of different functions in different products, and most of them need flexibility, thinness, and ultralow power consumption. These requirements can only be satisfied with new methods of packaging.
March 24, 2018 - San Diego, CA -
The 2018 IEEE 68th Electronic Components and Technology Conference (ECTC) takes place at the Sheraton San Diego Hotel & Marina, May 29 – June 1, 2018. Attendance at the past three editions of ECTC has consistently topped 1400. Sam Karikalan, the General Chair of the 68th ECTC, noted that with IC packaging increasingly playing the role of performance enabler in integrated circuits, the conference has also rightly gained the attention of major OEMs that are focused on scaling up their system performance. “The 68th ECTC is looking forward to playing the host again for all the world’s leading IDMs, wafer foundries, OSAT service providers, substrate and material vendors, equipment manufacturers, research institutions and universities that will be showcasing their cutting edge R&D in the field of microelectronics packaging over four full days,” said Karikalan.