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TECHNOLOGY TRENDS

An introduction to chiplet-based architectures

By John Park [Cadence]

T his article discusses three Heterogeneous integration and expensive design teams are also required

when designing a complex SoC at the
major t rends i mpacti ng
chiplets
t h e wo rld of a d v a n c e d
Now let’s talk more about chiplets. In
companies have been feeling this pain
semiconductor packaging. the face of performance, power, and area latest node. Department of Defense (DoD)
The first and primary focus of this article constraints and reticle limits, and with for a while now and are leading the way
is heterogeneous integration. The modern the cost of production at advanced nodes in finding design alternatives for single
version of the term has various meanings skyrocketing, many in the semiconductor monolithic SoCs.
to different people, but in this article, industry have shown increased interest Another important consideration is
heterogeneous integration is defined as in a disaggregated approach to chip that large reticle-size chips typically
a disaggregated system-on-chip (SoC) development. In other words, when cost don’t yield very well, again driving up
architecture built from multiple chiplets. and low volume come into play, SiP looks costs. Back around 2008, we saw an
This design approach is similar to a like the ideal alternative to designing an alternative when Xilinx partitioned a
system in package (SiP), except instead of advanced-node monolithic SoC. Gordon large field-programmable gate array
integrating multiple bare die (including 3D Moore was aware of the future possibility (FPGA) into four smaller, higher
stacking) on a single substrate, multiple of this disaggregated design approach yielding chips, and connected those
intellectual property (IP) in the form of (Figure 1) and predicted that, “It may chips together on a silicon interposer.
chiplets are integrated on a single substrate. prove to be more economical to build Arguably, this launched the 2.5D-
The second major trend involves new IC packaging trend that has become
silicon manufacturing techniques that commonplace today for high-bandwidth
leverage through-silicon vias (TSVs) and memory (HBM) processor integration.
high-density fan-out redistribution layers We can’t forget about analog and
(RDLs). These advancements are driving radio frequency (RF) devices, where
more silicon into the predominately leveraging Moore’s Law has never
laminate-based world of semiconductor been a big benefit, as scaling down in
packaging, especially when high bandwidth geometry makes some analog circuits
and form factor become key attributes of more challenging to design. This also
the design. This trend brings new design applies to today’s high-speed I/Os, which
and verification challenges with which are closer to analog design than digital.
most packaging engineers are not familiar
because they are not typically an aspect of Figure 1: A modularized SoC. The modularized SoC
laminate-based design. With traditional More-than-Moore
Finally, on the ecosystem side of things, large systems out of smaller functions, scaling coming to an end, many engineers
we see that all of the large semiconductor which are separately packaged and are considering a more modularized or
foundries now offer their own versions of interconnected.” For some applications, disaggregated approach to designing
advanced packaging. In many ways, this we have reached that inflection point. We an SoC. After all, we don’t want to lose
brings a breath of fresh air to the packaging are now in the age of “More than Moore.” the many benefits of IP reuse. Rather
community because of the use of new ways We all knew the day would come when than traditional hard or soft IP, we are
of supporting package design teams with Moore’s Law would come to an end. For talking about a physically realized and
assets like reference flows and process many applications, the end is already tested chiplet. These chiplets are key to
design kits (PDKs). Electronic design here. Starting back in 2012, the cost the next generation of More than Moore.
automation (EDA) companies are now per transistor had been steadily rising, This chiplet-based architecture allows
working with many of the leading foundries prompting many leading-edge companies designers to leverage IP without regard
and outsourced semiconductor assembly to start investigating alternatives to basing to the node or technology on which it’s
and test suppliers (OSATS) to develop everything on Moore’s Law. Companies manufactured. Designers can focus
multi-chip(let) packaging reference flows that don’t build hundreds of thousands solely on their IP or the value-add they
and package assembly design kits (PADKs). or millions of chips find it impossible to bring to the design. These chiplet-based
This additional infrastructure greatly recoup non-recurring engineering (NRE) designs can be built on many different
benefits the package design community. costs at the latest design nodes. Huge and materials such as silicon, glass and

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