Page 49 - ChipScale_Jul-Aug_2020-Digital

Figure 4: Key drivers of SiP vs. standalone package. SOURCES: [1,2]
References
1. “System-in-package technology and
market trends 2020” report, Yole
Développement, 2020.
2. “Advanced packaging technology in
the Apple Watch Series 4’s system-
in-package” report, System Plus
Consulting, 2019.
3. “Qualcomm QET5100M envelope
tracker module with SEMCO’s
e m b e d d e d d i e p a c k a g i ng
technology” report, System Plus
Consulting, 2019.
4. “NVDIA Tesla P100 GPU with
H BM 2” re por t, System Plu s
Consulting, 2017.
Figure 5: SiP commercialized products. SOURCES: [3-5] 5. Advanced system-in-package
For high-end SiP, the Nvidia Tesla CPUs. Deep learning training (comparing technology in Apple’s Airpods Pro”
V100 GPU is meant for data centers and 8X V100 & 8X P100 modules) can take report, System Plus Consulting, 2020.
is used to accelerate artificial intelligence 5x less time than with the Tesla P100
(AI), HPC and graphics. Tesla V100 GPU, and its deep learning inference Acknowledgment
c ome s i n 16 a nd 32GB me mor y (comparing 8X V100 & 8X P100 modules The authors wish to thank Stéphane
configurations and 900GB/s total & Xeon CPU) has 3X higher throughput Elisabeth, PhD, Technology & Cost
bandwidth, with power consumption of than Tesla P100 and is 7X more powerful Analyst at System Plus Consulting, for
250-300W. In a single GPU, Tesla V100 than a Xeon CPU. his contributions to this paper.
offers performance equivalent to 100

Biographies
Favier Shoo is a Technology and Market Analyst in the Semiconductor & Software division at Yole
Développement, part of the Yole Group of Companies. Based in Singapore, he is engaged in the development
of technology and market reports, as well as the production of custom consulting reports. He holds a Bachelor’s
in Materials Engineering (Hons) and a Minor in Entrepreneurship from Nanyang Technological U. (NTU)
(Singapore). He was also the co-founder of a startup company. Email: favier.shoo@yole.fr
Santosh Kumar is currently working as Principal Analyst and Director Packaging, Assembly & Substrates for
Yole Développement’s activities in Korea. He is involved in the market, technology and strategic analyses of the
microelectronic assembly and packaging technologies. He is the author of several reports on fan-out/fan-in WLP, flip-chip, and
3D/2.5D packaging and received Bachelor’s and Master’s degrees in Engineering from the Indian Institute of Technology (IIT),
Roorkee and U. of Seoul, respectively.

47
Chip Scale Review July • August • 2020 [ChipScaleReview.com] 47