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for high-performing SiP – rather, it is cost. SiP commercialized applications Tracker; Automotive ADAS advanced
Right now, chiplet technology is growing Based on our System Plus Consulting computing unit - Mobileye’s EyeQ4, and
exceptionally fast because advanced node tear downs of recently commercialized Nvidia Tesla V100 – GPU + HBM.
yield is not good (in short). For 7nm, 5nm, SiP products, the underlying common key In 2019, the latest AirPods Pro designed
and beyond, the fabrication cost for SoC is factor is essentially the ability to create and manufactured by Apple was the only
simply too high because of low yield, and it highly-integrated products in a smaller earphone in the market with an active
is not a wise business move. Some smaller package with increased functionality at a noise cancelling feature. Two SiP modules
players pushing node-scaling cannot lower cost. As examples, Apple’s AirPods are found inside the AirPods Pro (Figure
make any more chips right now. So cost Pro - SiP Audio Module; Fitbit Charge 3 5). The module has a special shape that
is the key and SiP cost is generally more (acquired by Google) - Microcontroller is designed in the shape of the opening of
attractive than that of SoCs, especially in + Bluetooth; Motorola 5G Moto Mod the human ear to maximize the comfort
the advanced nodes. - Qualcomm QET 5100 M Envelope of the AirPods Pro Earbuds. The SiP
Audio Module comprises two assembled
modules. The Audio Codec Module, H1
Module and MEMS Sensors are included
in the audio device. The modules contain
an audio amplifier that eliminates
background noise and produces clear
sound. The H1 Module contains the H1
®
chip/Bluetooth processor that enables
wireless connection and drives voice-
enabled Siri and enforces real-time noise
cancellation. The H1 chip has better
power management and increased talk
time compared to Apple’s previous W1
chip and uses a 16nm FinFET technology.
For the Fitbit Charge 3, Cypress
has combined two dies of different
functionality (a microcontroller with
®
Bluetooth ). This FO SiP is packaged by
JCET (STATS ChipPAC’s Singapore fab).
Die 1 - MCU is a CapSense (capacitive-
sensing) technology that measures changes
in the capacitance between a plate (the
sensor) and its environment, to detect the
presence of a finger on or near a touch
surface. Die 2 - BLE is a form of wireless
communication designed especially for
short-range communication.
In 2019, Samsung Electro Mechanic
(SEMCO) started the next wave with the
introduction of ED packaging technology
in the Qualcomm QET 5100 M for
Motorola’s Moto Mod 5G hardware and
Samsung’s S10 5G US-version smartphone.
The envelope tracker IC die is embedded
into the 6-layer PCB substrate. All the
passives are mounted on the surface of the
PCB substrate and overmoulded.
Within automotive, Mobileye’s EyeQ4
P is a computing unit used in level 3 ADAS
RoHS
vehicles that can process data from several
cameras as well as light detection and
ranging (LiDAR), and radar. The EyeQ4
unit is a type of simple SiP where the SoC
is packaged in the same package with a
few passives. The FC BGA SiP package is
done by STMicroelectronics in Malta. It is
noteworthy that EyeQ5 is in development
and is meant for ADAS level >3.

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