Page 18 - ChipScale_May-June_2020-digital

Ba c k s i d e a l i g n m e n t p l a y s a
substantial role when it comes to
bonded, opaque substrates or non-
transparent materials used in multi-
laye r a nd mu lt i- d ie pro ce ssi ng.
Referencing to the same structure
for multiple exposures also helps to
minimize misalignment as current
patter n design density increases.
Overlay errors or misalignment of any
kind impact the electrical properties
of c ont a c t s a nd i n s u lat ion , a nd
might create connection failures that
significantly affect fab yield, overall
productivity and cost of ownership
(CoO). Systems equipped with MLE
Figure 1: Critical dimension versus focus position for DoF process window evaluation.
tech nolog y i nteg r ate f u ll wafer
window perfor mance at 2µm L/S typically up to 16 alignment marks backside alignment (see Figure 3)
together with the simulated curve is (marked with blue and yellow), can utilizing dedicated objectives with near
displayed in Figure 1. be placed randomly in the layout in infrared (IR) capability and proprietary
On top of the exposure window, order to comprehensively cover the chuck design accommodating wafer
the relatively small exposure field and most critical areas on the substrate and sizes up to 300mm.
the <1µm precise autofocus extends compensate for global distortions.
the usable dynamic focused range
to more than 100µm. The ability to
control the focus position on a larger
scale of the wafer position via chuck
posit ion i ng a nd wafe r cla mpi ng
enables compensation for bowed and
warped substrates.

Dynamic exposure methods and Figure 3: Schematic drawing of top- and bottom-
active die-shift compensation side alignment objectives.
Cu r rent back- end lithog raph ic
s y s t e m s h a v e no c o n t r o l o v e r
distortions smaller than the exposure When considering the die distortion
field and therefore face difficulties errors induced after reconstitution
with nonlinear, high-order substrate on the wafer, as is typical for fan-
distortions and die-shift-related issues, out wafer-level packaging (FOWLP),
especially after die reconstitution on the advanced distortion functionality
the wafer. MLE employs dynamic Figure 2: Advanced distortion compensation should also be applied at the die
alignment modes with an automatic schematic process flow. level, where active compensation
fo c u s , i n o r d e r t o a d a p t t o t h e and rerouting results strictly rely on
s u b s t r a t e m a t e r i a l a n d s u r f a c e After misalignment measurement, external metrology data. Distortion
variations. The advanced distortion displacement vectors are f ur ther compensation algorithms include
functionality relates and analyzes compiled in parallel before the design is mathematical correction of rotation,
real-time data from synchronized interpolated and rendered in real-time. scale, shear and translation (shift). For
visible or near-infrared topside and The exposed patterns are therefore fully die-placement-error compensation,
backside alignment. It accomplishes error-compensated without inducing the model limits distortions within
this by actively compensating for overlapping or noncovered regions – the dies to the rigid body of the die,
mechanical die placement, stress- delivering minimum misalignment which typically is represented by
induced inaccuracies such as rotation, with no impact to the throughput of two (external) alignment points per
displacement, expansion and high- the patterning process. A visualization die. Because of the immediacy of
order distortions of the substrate. The of a compensated layout (dark grey) the conversion process, the dynamic
process flow of the advanced distortion after an extreme atypical misalignment binary pattern generation complements
cor rection f unction and dynamic (indicated with red arrows) example is externally acquired metrology data
alig n ment modes a re v isu ali zed shown as a result after compensating of each die individually per substrate
in Figure 2. Dynamic alignment the actual position of 16 marks (yellow) just before the exposure in order to
includes both global as well as multi- of multi-point alignment through the compensate for overlay/positioning
point wafer alignment options, where dynamic alignment mode. errors caused by handling or pre-

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