Page 17 - ChipScale_May-June_2020-digital

Maskless lithography addresses shift to 3D integration

By Bozena Matuskova, Boris Považay, Frank Bögelsack, Roman Holly, Tobias Zenger, Thomas Uhrmann,
Bernhard Thallner [EV Group]
T he continuous development mix adds to multiple masking levels, finer critical dimensions. In contrast,

a n d c a p a b i l i t y o f
lit hog raph ic pat ter n i ng and correspondingly masks and mask h ig her NA reduces t he de pt h of
focus (DoF). Finding a compromise
inventory/cleanroom storage represent
e q u i p m e n t f or s e m i c on d u c t or a high portion of overall production between resolution and focal depth
manufacturing is driven by several costs. Additionally, replacement costs is often a decisive parameter for the
megat rends that are shaping ou r for conventional laser sources or Hg interconnect circuit design. This is
digital society. As 2D-IC density lamps can add up to significant levels. especially true in advanced packaging
scaling is reaching its cost limits, The wait time for new physical mask as reconstitution of wafers is a central
especially for the patterning processes, sets as well as overall proof of new element in integrating die from various
advances in miniat u r ization and design concepts for high product-mix wafer manufacturers in a multi-die
device performance are currently designs intrinsically lead to prolonged solution. Apart from those physical
being extended toward 3D integration development cycles for conventional limitations, inaccuracies from die
and heterogeneous integration (HI) mask-based production environments. placement and die shift variations
within advanced packaging. This These requirements triggered the c au s e d by ove r-mold i ng a d d a n
novel approach is seen as a key enabler development of our maskless exposure additional layer of difficulty with
for next-generation devices, wherein (MLE™) technology to resolve critical which current lithography steppers
mobile processors have triggered a needs in semiconductor packaging. and other mask-based systems struggle
first growth cycle in 3D/HI. This MLE technology directly tackles this to cope. In addition, the given reticle
growth cycle is expected to continue crucial demand for design flexibility size and optics dimensions of static
as high-performance applications while enabling scalability in both exposure systems limit the exposure
such as artificial intelligence (AI) and development and production facilities area. T his sit uation can become
5G gain traction in mobile devices, – thereby shortening development particularly challenging for larger
but also due to other megatrends cycles between R&D and production die inter poser fabrication, where
such as autonomous driving, which p h a s e s – b y el i m i n a t i n g m a s k- stitch lines or mismatched overlap
necessitates high reliabilit y and related difficulties and consumables regions of reticle exposure fields can
data network capacity, as well as the costs. The technology features high- affect electrical properties within the
Internet of Things (IoT). resolution (<2µm L/S), stitch-free, redistribution layer (RDL). The ability
Advanced packaging technologies dynamically addressable exposure of to generate a stitch-less pattern for
have both increased in complexity, the entire substrate surface, which interposers exceeding current reticle
as well as in the number of options enables agile processing and low cost size is increasingly important for
over the years. Transformation from of ownership (CoO). advanced devices needed for complex
single- to multi-die packaging, enabled layouts, such as in advanced graphics
by 3D integration, is one example, Limitations of traditional processing, AI and high-performance
which addresses the challenge of exposure methods computing (HPC).
h a nd l i ng big d at a ge ne r at e d by Fundamentally, the resolution of any MLE addresses these needs through
high-performance computing. The optical imaging system is determined a combination of sub-nanometer-range
continuous in novation of chiplet by the ratio of exposure wavelength stage motion accuracy, distortion-
design and variety of integration and its numerical aper ture (NA). free, high-intensity optics and real-
schemes (on silicon, embedded or in By definition, NA defines the light- time patterning of a vector-based mask
package) can finally include several gathering and light-emitting ability file. For reference, other approaches
pat ter ning levels. The increased through the lens, and is characterized that need to rasterize the mask image
importance of design flexibility and by the angle of aperture and thereby prior to patterning, generate in the
the ability to adopt both die- and highly dependent on focal length. range of 141GB of data for every
wafer-level designs simultaneously in Tech nically, alteration of NA in 300mm wafer. Finally, the digital
back-end lithographic processing have exposure systems tends to be more cost mask pattern is projected with sub-µm
to be addressed because of the need to effective than shortening the ultraviolet accuracy onto the substrate surface.
shorten development cycles and cover (UV) wavelength of the light source. Like most modern lenses, the MLE
the wide variety of advanced packaging Imaging exposure systems (such as imaging system is diffraction-limited,
pl a t fo r m s a t t h e s a m e t i m e. I n steppers) are typically driven toward and it supports a DoF of ±12µm. A
addition, any advanced product design higher NA to enable structuring of measurement of the DoF process

15
Chip Scale Review May • June • 2020 [ChipScaleReview.com] 15