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Measuring bump height uniformity to improve yield

using 3D inspection

By Tim Skunes [Nordson Test & Inspection]

C h i p - s c a l e w a f e r- l e v e l When design rules change and yield Conventional bump height

packaging (WLP) offers
i m p o r t a n t b e n ef i t s — d rops, it becomes appa rent t hat measurement
reducing inspection does not save
Pillar bumps consist of three layers:
small package size and the ability time in the long run. The best way to a copper pillar, a nickel barrier layer,
to process hundreds or thousands improve yield, especially for a new and a tin/silver/copper (SAC) solder
of dies i n parallel. A var iet y of process, is to identify defects early. bump. Bump height measurements
bump configurations are possible, That often requires 100% inspection are typically taken after the final
depending on the application, as across each wafer in every batch. photoresist stripping step, as shown in
shown in Figure 1 [1]. One challenge Stringent inspection protocols help Figure 2. This occurs after all three
with WLP is maintaining uniformity identify the root cause of defects layers of the bump have been deposited.
of solder bumps or copper pillars and reduce the need to rework or Conventional noncontact bump
across a 300mm wafer. Metrology scrap wafers. height measurement relies on line
a nd i nspect ion a re necessa r y to Existing bump height measurement scan triangulation. An incident beam
ensure device reliability. Shrinking methods have two drawbacks: speed of laser or white light def lects off
b u m p h e i g h t s a nd s p a c i n g a nd and placement in the process f low. the object being measured. With line
high aspect ratios, however, make They slow down production and often scan triangulation, the light source
wafer-level bump height inspection do not catch defects early enough in projects a line onto the object. A
especially challenging. It is also the process. While 100% inspection detector with an array of photosensors
increasingly critical because minor is com monpla ce du r i ng pro ce ss captures the reflection and calculates
variations in bump height across development, it is often abandoned the distance. Scanning across a wafer
a wafer can reduce overall yield. for high-volume production because produces a map of bump height data.
Defects related to bumping can affect of the time required for testing. Fast, Li ne scan t r iang ulat ion has t wo
both thermal and electrical device accurate metrology and inspection primary drawbacks. One of these is
performance [2]. are the key to success. This article speed. A 300mm wafer can contain
It can be tempting to cut down on explains the benefits of 3D fringe hundreds of millions of copper micro
the number of inspection steps or projection tech nolog y to inspect bumps [3], and 100% inspection is
only test a sample of wafers coming solder bu mps and copper pillars not economical.
through the line. Doing so can speed at the wafer level, comparing it to The other drawback to line scan
up production. For legacy processes conventional approaches for bump triangulation is that it happens too
where the yield is high, a partial height measurement. late in the manufacturing process.
inspection may be the best approach. Inconsistent copper plating is often

Figure 1: Evolution of bump size and pitch. Image courtesy of T. Tick and S. Vahanen [1]

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