Page 48 - Chip Scale Review_November December_2022-digital

modeling work indicates that the self- step needed to pattern the nTSVs on the significant reduction in alignment errors
heating effect can, to a large extent, be wafer’s backside. More specifically, it and distortion values. In addition, by using
countered by the metal lines in the wafer’s challenges the precision with which the advanced lithography correction techniques,
backside, which provide additional lateral nTSVs need to be aligned to the bottom BPR the overlay error of the nTSV lithography
thermal spreading. More detailed thermal layer. Because we are dealing with features with respect to the BPR structures can be
simulations are currently ongoing to gain that are of standard cell dimensions, the reduced to less than 10nm.
more insights [6]. overlay requirement should be better than
Wafer bonding: precise nTSV/BPR 10nm. Conventional lithography alignment No degradation of device
alignment. The wafer bonding step cannot, however, sufficiently compensate for performance
inherently distorts the first “active” wafer. the wafer distortion. Fortunately, advances One important question remains: are
This distortion challenges the lithography in wafer-to-wafer bonding allow for a the newly added process steps, such as
BPR integration, wafer thinning, and
nTSV processing, impacting the electrical
performance of the devices fabricated in
the front-end? To answer this question,
imec recently built a test vehicle using the
fabrication flow and the improved process
steps described above. In this test vehicle,
scaled FinFETs connect with tight overlay
control to the wafer’s backside through
320nm-deep nTSVs landing on BPRs
(Figure 6). The BPRs also connect to the
frontside metallization through the M0A
layer and V0 via. This frontside connection,
among others, allowed researchers to assess
the electrical performance of the devices
before and after backside processing. With
this test vehicle, imec showed that FinFET
performance was not degraded by BPR
implementation and backside processing,
provided that an anneal step is performed at
the end to get optimal device properties [4].
Application to logic ICs and
3D-SoCs
Some chip manufact urers have
publ icly a n nou nced i nt roduci ng
BSPDNs in logic ICs of the 2nm and
beyond technology node. This is when
nanosheet transistors are making
inroads. However, the novel routing
technology can be used for a broad
range of transistor architectures. Imec’s
roadmap foresees its introduction
in advanced technology nodes, with
nanosheet transistors in 6T standard
cells. The combination with BPR will
then help push standard cell heights
below 6T. The application domain,
however, extends beyond just 2D single-
P chip ICs: it also holds promises for
RoHS
the performance improvement of 3D
systems-on-chip (3D SoCs).
Imagine 3D-SoC implementation
where some or all memory macros are
placed in a top die while logic is placed
on a bottom die. On the technology
side, this can be realized by bonding
the active frontside of the “logic wafer”
to the active frontside of the “memory

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46 Chip Scale Review November • December • 2022 [ChipScaleReview.com]