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n-TSVs and its potential as a      IEEE 72nd Elect ronic Comp.        Interconnect Tech. Conf. (IITC),
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            Tech., 2021, pp. 1-2.              pp. 1531-1538, doi: 10.1109/       IITC51362.2021.9537541
          4.  A. Veloso, et al., “Scaled FinFETs   ECTC51906.2022.00244         8.  [8] R. Chen, et al., “Backside PDN
            connected by using both wafer    6.  [6] H. Oprins, et al., “Package   and 2.5D  MIMCAP to double
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                       Biographies
                         Naoto Horiguchi is the Logic CMOS Scaling Program Director at imec in Leuven, Belgium. He obtained
                       a degree in Applied Physics in 1992 from Tokyo U., Japan. He has been with imec since 2006, where he
                       is engaged in advanced CMOS device R&D together with worldwide industrial partners, universities, and
                       research institutes. His current focus is CMOS device scaling down to 1nm technology node and beyond. Email
                       naoto.horiguchi@imec.be

                         Eric Beyne is a Senior Fellow, VP of R&D, and Program Director of 3D System Integration at imec in
          Leuven, Belgium. He obtained a degree in electrical engineering in 1983 and a PhD in Applied Sciences in 1990, both from the
          KU Leuven, Belgium. He has been with imec since 1986, working on advanced packaging and interconnect technologies.


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