Page 49 - Chip Scale Review_November December_2022-digital

wafer.” In this configuration, the bonding, wafer thinning, and nTSV 51, Sept. 2021, doi: 10.1109/
original backsides of both wafers now processing, are gradually being improved, MSPEC.2021.9531012
reside on the outside of the 3D-SoC thereby preparing the new routing 2. S. K. Moore, “Arm shows backside
system (Figure 7). We can now think technology to introduce in advanced logic power delivery as path to further
of exploiting the “free” backside of the technology nodes and future 3D SoCs. Moore’s Law,” IEEE Spectrum,
“logic wafer” to deliver the power to 2019; https://spectrum.ieee.org/
the power-hungry core logic circuits. References a r m - shows - b a ck sid e - p owe r-
This can be accomplished in the same 1. B. Cline, et al., “Power from del ive r y-a s -pat h-t o -f u r t he r-
way as proposed for 2D SoCs. The below: buried interconnects will moores-law
main difference with this configuration help save Moore’s Law,” IEEE 3. A. Veloso, et al., “Enabling logic
is that the original dummy blanket Spectrum, vol. 58, no. 9, pp. 46- with backside connectivity via
wafer – earlier introduced to enable the
wafer thinning – is now replaced by
a second, active wafer (in this case, a
memory wafer).
Although the design noted above is
yet to be implemented experimentally,
first assessments from the IR drop
perspective are very encouraging. The
proposed solution was validated on a
memory-on-logic partitioned design LEADERS IN
using an advanced node research
process design kit (PDK). Implementing MICRO DISPENSING
a BSPDN w it h nTSVs a nd BPR s
showed promising results: 81% and 77% TECHNOLOGY
average and peak IR drop reduction
for t he bot t om d ie compa re d t o SMALL REPEATABLE VOLUMES
conventional frontside power delivery. ARE A CHALLENGE, BUT NOT
This makes backside power delivery IMPOSSIBLE IF YOU HAVE BEEN
ideal for 3D-IC power delivery in CREATING THEM AS LONG AS WE HAVE.
advanced complementary metal-oxide
semiconductor (CMOS) nodes [7].
For both 2D and 3D designs, the
concept of exploiting the wafer’s free TO DO IT WELL,
backside can potentially be expanded
to other functions by adding specific WE PROVIDE THREE THINGS:
devices in the backside, such as I/Os or
electrostatic discharge (ESD) protection
devices. Imec, for example, combined
backside processing with implementing Dispensing Expertise in a variety of microelectronic
a 2.5D (i.e., pillar-like) metal-insulator- packaging applications.
metal capacitor (MIMCAP), which
serves as a decoupling capacitor. The Feasibility Testing & Process Verification based
2.5D MIMPCAP boosts capacitance on years of product engineering, material flow testing
density with a factor of 4 to 5, allowing and software control.
a further improvement of the IR drop.
The results were derived from an IR Product Development for patented valves,
drop modeling framework calibrated dispensing cartridges, needles, and accessories.
with experimental data [8].

Summary
Future chips may well break the
tradition of delivering power through
the frontside. A BSPDN with backside Our Micro Dispensing product line is proven and trusted by
metals, buried power rails, and nTSVs manufacturers in semiconductor, electronics assembly, medical
has shown clear advantages in reducing device and electro-mechanical assembly the world over.
the IR drop, releasing the BEOL routing www.dltechnology.com.
strain, and improving standard cell
height scaling. The critical process
steps, including BPR integration, wafer 216 River Street, Haverhill, MA 01832 • P: 978.374.6451 • F: 978.372.4889 • info@dltechnology.com

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