Page 28 - Chip Scale Review_November December_2022-digital

Device validation: the ultimate test frontier

By Dave Armstrong [Advantest America, Inc.]

I n the early days of space exploration, functional validation that typically involved Method 3: structural test

spacecraft were manned by small
As ICs became more digital, scan
teams of one to three astronauts. five elements: chains provided a standard way to access
Notably, most of these astronauts were 1. Instruments connected to primary the innards of the DUT, and automatic test
experienced test pilots who intimately device inputs and outputs; pattern generators (ATPGs) addressed the
understood the vehicle they were flying and 2. Instruments to program the device tedious pattern-generation challenges. The
the interaction between all the variables into its various modes of operation and use of ATPGs was highly successful over
controlling the craft. Similarly, early environmental extremes; the years because of multiple factors:
integrated circuits (ICs) were created 3. A tangle of wires to interconnect
by small teams of engineers, who often instruments, the device under test • It was automatic;
designed, laid out, and even developed (DUT), and a test-system controller; • It provided a testability baseline
tests for their devices. Notably, the tests 4. An intelligent operator (often involving that defined a minimum acceptable
were most often functional, and the test the chip designer) who controlled quality level;
interfaces were often analog. Over the years, the setup to pinpoint problems and • It leveraged a consistent DUT
ICs have become much more complicated, determine optional operations; and interface that then drove consistent
and team size and group effort have grown 5. A test controller program typically instrument interfaces;
exponentially. Given the resource and cost coded in some proprietary test scripts. • It worked well in a distributed
constraints, it’s rapidly becoming clear that engineering environment; and
the fundamental limitation to continued While the picture of a functional • Enhancements such as pattern
industry growth is no longer gate length, but validation setup hasn’t changed much compression and homogeneous-core
team size and strength. over the years, the increasing complexity pattern sharing allowed test costs to
Contending with unconstrained growth of the devices and relentless time to scale slower than Moore’s Law.
in test data volume, as well as effort, market (TTM) pressure resulted in a need
requires a vision for taming this growth for multiple setups enabling concurrent As device complexities grew, so did
in the not too distant future. That vision engineering. Note that the need for the test data volume needed to traverse
must focus on intelligent application of new functional device validation does not the logic and confirm proper logic cell
innovations in pre-silicon validation, first- go away with first customer shipments. operation. The “International Technology
silicon “bring-up,” post-silicon validation The experts will need their test setups Roadmap for Semiconductors” (ITRS)
(PSV), software-driven functional test, when called upon again to help with yield tracked this ever-increasing data volume,
and production test. The challenge, investigations and field returns. shown in blue in Figure 1, which also
paraphrasing Star Trek, is to boldly go shows the number of transistors per large
where no test solution has gone before. Method 2: functional test at ATE logic device [1] in green and announced
The first half of this paper describes how The first automatic test equipment chips [2] with purple points. The ITRS-
the industry has developed four different (ATE) tests were all functional. Some calculated [1] flat file test data volume is a
validation and test methods and how their argue that the most valuable ATE- conservative indication of the effort needed
values and focus have shifted over time. based tests, even today, are functional. to support this test generation effort (a 14x
This exercise pinpoints the effort needed as These tests on the ATE use a few well increase in the last decade).
a function of circuit density. The latter half understood instruments interconnected A review of Figure 1 indicates that the
discusses the limited growth of tools and through a tightly controlled device under structural test generation effort is growing
methodologies in the functional testing and test (DUT) interface to confirm to the even faster than Moore’s Law. As the
PSV area and the skyrocketing growth in extent possible the proper operation of the levels of logic grow deeper and deeper it
the required effort. However, by leveraging device in mission mode. Functional tests takes more and more vectors to gain the
some of the best practices of the past – such on ATE are typically analog, measuring controllability and observability necessary
as standard interfaces, automation, and parameters such as Vmin and Fmax to effectively test the part, as shown in
scalability – we will be able to streamline over temperature extremes. What ATE Figure 2, which plots the ratio of the two
first silicon “bring-up” moving forward. functional test cannot do is run tests that lines in Figure 1.
require attached memory, peripherals, Many industry participants, including the
Method 1: device validation/ or both. This lack of full-functional test author, feel that Figure 2 suggests we are
characterization coverage has driven the recent rise in the fighting a losing battle with structural test.
A small group of product experts use of system-level test (SLT), discussed While introduction of new on-chip fabrics to
performed early device testing and in method 4, below. more efficiently transport structural test data

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