Page 27 - Chip Scale Review_November December_2022-digital

Reliability performance. After optimizing the RDL design, shown in Table 5. After reliability testing, failure analysis was
the fan-out packages were subjected to the standard JEDEC performed to check the integrity of the C4 joints and fine-line
reliability tests including moisture soaking level 4 (MSL4) as patterns in the RDL layers. Cross-sectional analysis of the units
preconditioning, temperature cycling test (TCT) with -40°C to showed no bump cracks or trace cracks (Figures 13 and 14).
125°C (condition G), uHAST with 110°C/85%RH, and high-
temperature storage test (HTS) at 150°C. Both packages passed Summary
6X multi-reflow and the reliability tests without any failures as The reliability of large multi-chip fan-out packages was evaluated
using the multi-reflow and component-level stress tests. Our study
showed that package stresses from thermal loading could cause RDL
cracking in the metal traces interconnecting the dies. The RDL trace
locations near the gap between the SoC and I/O die are high stress
concentration areas. RDL trace design and geometric dimensions
are critical to interconnect reliability. Thicker and/or wider traces
reduce the risk for RDL cracking. Increasing the distance between
the trace via and the turning point in the line also reduces the RDL
crack risk. By optimizing the RDL design and trace dimensions,
RDL stress effects can be minimized enabling large-format fan-out
packages to pass the standard JEDEC reliability tests.

Acknowledgments
The authors thank TSMC for its assistance with finite element
stress simulations. Portions of this paper were presented at
ECTC 2022.

References
1. Y. H. Lin, et al., “Multilayer RDL interposer for
heterogeneous device and module integration,” IEEE
Figure 13: Cross section showing good copper pillar C4 joint integrity. 69th Electronic Components and Technology Conference
(ECTC), 2019, pp. 931-936.
2. Y. P. Chiang, et al., “InFO_oS (Integrated Fan-Out on
Substrate) technology for advanced chiplet integration,”
IEEE 71st ECTC (2021), pp. 1-6.
3. G. J. Scott, et al., “Heterogeneous integration using organic
interposer technology,” IEEE 70th ECTC (2020), pp. 885-892.
4. S. Y. Hou, et al., “Wafer-level integration of an advanced
logic-memory system through the second-generation
CoWoS technology,” IEEE Trans. Electron Devices, vol. 64,
no. 10, pp. 4071–4077.
5. D. C. H. Yu, “Advanced packaging with greater simplicity,”
2017 IEEE International Electron Devices Meeting (IEDM),
IEEE Press, Dec. 2017, pp. 3.6.1-3.6.4.
6. C. Wang, et al., “Signal integrity of submicron InFO
heterogeneous integration for high-performance computing
applications,” IEEE 69th ECTC (2019), Las Vegas, NV,
USA, pp. 688-694.
7. T. C. Wang, et al., “RDL layout pattern reliability analysis
and optimization with TCAD stress modeling,” IEEE Inter.
Figure 14: Cross section of the RDL structure. Interconnect Tech. Conf. (IITC), 2017, pp. 1-3.

Biographies
Laurene Yip is a Technical Manager at MediaTek Inc., San Jose, CA. She has over 30 years of experience in
the electronics industry focusing on development and qualification of flip-chip, fan-out wafer-level, and 2.5D/3D
packaging. She has over 20 patents and publications related to advanced packaging and reliability. Email
laurene.yip@mediatek.com.

Rosa Lin is a Technical Manager at MediaTek Inc., Hsinchu, Taiwan, with more than 10 years’ advanced
packaging experience. She has deep understanding of material characterizations, and processes and reliability
of 2D, 2.5D and 3D packaging. By focusing on new development and applications, she also obtained over 10 patents and
publications related to advanced packaging technology.

25
Chip Scale Review November • December • 2022 [ChipScaleReview.com] 25