Page 14 - Chip Scale Review_Jul Aug_2022-digital

Vertically-integrated packaging solutions driven

by innovations

By Mark Gerber, Lihong Cao, Vikas Gupta, Patricia MacLeod [ASE, Inc.]
A s Moore’s Law continues ASE has developed a series of RDL- layer (RDL) as compared to substrates, and

to challenge the foundry
compa n ies to i ncrease based vertically-integrated packaging 2) a shorter interconnect length resulting
in better electrical performance, and 3) a
solutions that continue to evolve to meet
transistor density, new performance and these various challenges. The six pillars smaller/thinner form factor because the fan-
cost challenges are driving the need for underneath the VIPack™ platform include: out technology allows die I/O signals to be
heterogeneously integrated (HI) advanced fan-out system-in-package (FOSiP), fan-out fanned out to a region larger than the die area
packaging solutions. Advanced silicon chip-on-substrate (FOCoS), fan-out chip- without an organic substrate to meet a higher
node yield attainment is a key driver for on-substrate bridge (FOCoS-B) (embedded), I/O count.
looking at ways to approach intellectual fan-out package-on-package (FO-PoP), Figure 1 shows a FOPoP package with the
property (IP) block integration. The high 2.5D/3D and co-packaged optics (CPO). cross-section image showing the die, RDLs,
development cost and lower yields are Each one of these package pillars addresses and Cu post details. Additional cross-section
challenging designers to look for new ways specific performance and/or form fit details are included in Figure 2, where the
of disaggregating system on chips (SoCs), challenges and provides advanced solutions active side of the die utilizes two routing
to reduce the die size, by separating IP that address the market segments listed planes to fan out the I/O signals. Fine-pitch
blocks that may not need to be in the most above. Packaging innovation within these Cu posts are used on the periphery to enable
advanced silicon node. Creating a SoC-like six technology pillars are being evolved electrical connections for the package on top.
solution with optimized silicon nodes for by ASE and these will be reviewed in the The FOPoP package platform is further
different portions of the chip is a new key sections below. enhanced for increasing complexity and
focus. Advanced redistribution layer (RDL) high-performance needs by enabling RDL on
packaging technologies that add a vertical FOPoP both sides of the die for increased integration
integration element allow for a denser, 3D Over the last decade, the trend for most and functionality. Furthermore, both land-
approach. At the same time, the traditional handheld consumer devices development side caps and near-die deep trench capacitors
packaging components, such as substrates, was towards multi-functional, high- (DTC) can be implemented to meet the power
are also being pushed to limits in which definition display, low power consumption, integrity requirements of advanced nodes.
new solutions are needed to extend roadmap high perfor mance, and thin /light FOPoP is, and will continue to be, a key
requirements. These roadmap requirements packages, that are now commonly found in package platform for application processors,
are seen across all industry market segments smartphones, tablets, and wearables. This mobile/auto antenna-in-package (AiP), and
including server, networking, graphics, trend drove the development of complex 3D co-packaged silicon-photonics applications.
mobile and telecom infrastructure. or 2.XD integration on integrated circuit
Each market segment has unique (IC) packages. Flip-chip package-on- FOCoS
requirements to meet its product needs and package (FCPoP), initially with traditional The advances in fan-out technology
there are a few common challenges across C4 solder bump and later with fine-pitch further provided opportunities to address
all of these segments. For example, as Cu pillar, was the primary package used the limitations of traditional flip-chip
advanced silicon nodes continue to shrink because of the inherent low-inductance packages where a single SoC is assembled
the die size and increase the power density package interconnect. on a substrate. Two distinct categories are:
per square mm, the challenge of signal The ever-increasing need for higher
noise increases dramatically. In addition, performance and thinner form factor drove 1. Utilizing the fan-out RDL process
the impedance challenges of connecting the accelerated implementation of FOPoP in to redistribute the die-level I/Os to
one chip to another in a system dramatically the mobile processor application space. The a coarser bump pitch to utilize less
reduces the performance that can affect fundamental high-density, substrate-less aggressive substrate design rules and/
battery life, or power requirements in configuration of the FOPoP package results or to reduce the number of layers on
an array bank of processors. The higher in higher package performance because of the substrate. This approach also helps
density per area of transistors and reduced the elimination of the substrate parasitic with low-k reliability issues related to
line to carry power also challenge the inductance along with a thinner package chip-package interactions.
thermal capabilities of the package— form factor. 2. Multi-die and chiplet integration
and when combined with other areas of Overall, the FOPoP structure provides where two or more dies can be
impedance in the system, can create larger 1) higher interconnection density and reconstituted into a fan-out module
system-level problems. integration through a finer L/S redistribution and then assembled on a substrate.

12 Chip Scale Review July • August • 2022 [ChipScaleReview.com]
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