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TECHNOLOGY TRENDS

Overcoming thermal wafer test challenges

for SoC and chiplet stacks

By Markus Kindler [ATT-Systems] Amy Leong [FormFactor Inc.]

L eading-edge artificial intelligence (AI)/graphic/ of cooling mediums: air-cooled or liquid-cooled.

mobile processors, dynamic random access memory
Figure 1 compares the maximum cooling capacity of air-
(DRAM) devices, and heterogeneous integrated and liquid-cooled configurations at a testing temperature
IC stacks are all facing the same set of thermal management of -40°C. The cooling capacity is a function of the specific
challenges, i.e., the device under test (DUT) is too hot to test. heat capacity, the thermal mass and the applied ΔT (i.e., the
Even at room temperature wafer chuck settings, a mobile difference between the coolant inflow temperature and the
system-on-chip (SoC) device junction temperature can reach coolant outflow temperature).
between 100°C to 150°C. For full-wafer DRAM testing, up to The lowest possible coolant temperature in air-cooled
2,000W of power may be applied during a single touchdown chillers available today is limited to around -80°C. The
test. Recent technology roadmaps show even higher heat cooling outflow temperature is basically determined by
dissipation requirements ranging up to 3,500W. With the rise the testing temperature, which is -40°C in this example.
of heterogeneous integrated chiplet stacks, test cell thermal Assuming a typical air-flow of 320 l/min, the given ΔT of
management becomes even more complicated. When testing 40K, and the properties of air, the calculated maximum
the base die with multiple chips stacked on top, the thermal cooling capacity is nearly 275W. Looking at properties
loading per silicon area is increased by an order of magnitude. of a thermal fluid, it is obvious the thermal mass of the
If the temperature is not controlled, it can result in burnt liquid coolant is >40 times higher than air, resulting in a
probes, damaged devices, and inaccurate test results. substantially higher maximum cooling capacity.
The temperature cannot be controlled unless it is first The example below is showing an inf low coolant
measured. ATT-Systems’ (a FormFactor company) low thermal temperature of -50°C. The testing temperature is at -40°C,
resistance (LTR) wafer chuck technology applies multiple which results in a ΔT of 10K. Using the same equation as for
temperature sensors across the thermal chuck to accurately air-cooled systems and a coolant flow rate of 10 l/min, the
detect DUT temperature and adjust heat dissipation to achieve calculated maximum cooling capacity is 3,300W, even the ΔT
the desired test temperature. LTR has shown promising results is remarkably lower. A lower ΔT leads to significantly better
in production test to address the “too hot to test” challenge. temperature uniformities, which is equally important for
current state technologies. Moreover, the cooling capacity can
Selecting the optimal wafer chuck system be scaled up by applying more powerful chillers. In summary,
A wafer chuck system consists of a wafer chuck, a controller, liquid-cooled systems give an order of magnitude higher
and depending on the application and temperature range, an air cooling capacity with better temperature uniformities and are
booster, or either a liquid- or air-type chiller. Without a chiller, the systems of choice for high-power applications.
the thermal chuck systems can control temperatures between After selecting the cooling mechanism, the next critical
+20°C and +200°C. For cold testing, chillers have two options design consideration is active thermal control (ATC).

Figure 1: Cooling capacity comparisons between a) air and b) liquid-cooled systems.

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