Page 33 - Chip Scale Review_May June_2022-digital

Better performance/improved
architecture: best yield
The goal of the signal deliver y
improvements described above is
opt i m i zat ion of the overall cost
function. Traditionally, semiconductor
test has been viewed as an added “cost
of quality.” Many hours are devoted
to highly optimizing the test process
to reduce the cost of test, either by
increasing throughput or lowering overall
capital costs for the test cell and fixtures.
The key is focusing test on optimizing
yield through a balanced strategy of
data analytics and yield learning, higher
performing test solutions with improved
accuracy and wider guard bands, or using
test for trim and repair.
As seen in Figure 5, a breakout of a
typical device, even on a relatively high-
yielding device, a minor improvement in
yield (in this case 1%), produces almost
10x the impact of the typical test cost
optimizations, like reducing the hourly
test cell cost, improving the overall test
throughput by shortening the test time, or
increasing parallel test efficiency.
As the semiconductor indust r y
ma rches for wa rd on t he pat h of
technological advances, the economics
of the manufacturing process must adapt
to the higher costs of the silicon used
to implement it. The path to achieve
the best possible yields is enabled by
the best possible ATE architectures
integrated with the best possible
interface performance.

Reference
1. K . R u p p , “ 4 0 Y e a r s o f
Microprocessor Trend Data,”
Retrieved at: Our World in Data;
https://ourworldindata.org/grapher/
transistors-per-microprocessor

Biographies
Tucker Davis is the Product Manager for UltraFLEX plus , at Teradyne, North Reading, MA. He is focused
on complex digital devices, such as mobile application processors. Prior to joining Teradyne, he was an
Applications Engineer and Product Manager for National Instruments. Tucker holds a Master’s degree in
Electrical Engineering from the University of Oklahoma, where he graduated summa cum laude. Email: tucker.
davis@teradyne.com
Brian Brecht is an Engineering Manager at Teradyne, Agoura Hills, CA. With more than 25 years of
experience in the design of automated test equipment instruments and platforms. He holds a number of patents
and has led design teams around the world in the delivery of high-performance device interface boards. In his current role, he is
focused on advanced interface structures for testing next-generation devices.

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