Page 48 - Chip Scale Review_March April_2022-digital
P. 48

“An overview of the development    integrated fan-out PoP (InFO_PoP)   IEEE 16th Electronics Packaging
             of a GPU with integrated HBM       technology for next-generation     Tech. Conf. (EPTC), Singapore,
             on silicon interposer,” IEEE 66th   mobile applications,” IEEE 66th   2014, pp. 318-321, doi: 10.1109/
             ECTC, Las Vegas, NV, USA, pp.      ECTC 2016.                         EPTC.2014.7028303.
             1439-1444, May 31-June 3, 2016.  27.  J. H.  Lau,  Fan-out wafer-level   36. R.  Tummala,  Fundamentals of
         18.  S. Ramalingam, “3D-ICs: advances   packaging, Springer Singapore,    Device and Systems Packaging:
             in the industry,” CPMT Seminar,    2018.                              Technologies and Applications,
             Latest Advances in Organic      28. R . Tu m m a l a , e t a l., “Gl a s s   McGraw Hill Professional, 2019.
             Interposers, Lake Buena, Vista, FL,   panel packaging, as the most   37. M-F. Chen, et al., “System on
             USA, May 27-30, 2014.              l e a d i ng - e d g e p a c k a g i ng :   Integrated Chips (SoIC™ for 3D
         19.  Mitsubishi Gas Chemical Company,   technologies and applications,”   heterogeneous integration,” IEEE
             Inc.; www.mgc.co.jp/eng/products/   Pan Pacific Microelectronics      69th ECTC 2019.
             /hfbt.html, Low CTE Laminate       Symp. (Pan Pacific), HI, USA,   38. Y. H. Chen, et al., “Ultra-high
             Substrates.                        2020, pp. 1-5, doi: 10.23919/      density SoIC with sub-micron bond
         20. H. T. Holden, D. Barr, D. Powell,   PanPacific48324.2020.9059521.     pitch,” IEEE 70th ECTC 2020.
             “Laminate/HDI Die Carriers,” in:   2 9. S . M u k ho p a d h y a y, e t a l. ,   39.  S. Ravichandran, et al., “Low-cost
             Puttlitz K.J., Totta P.A. (eds) Area   “Heterogeneous integration for   non-TSV based 3D packaging using
             Array Interconnection Handbook.    artificial intelligence: challenges   glass panel embedding (GPE) for
             Springer, Boston, MA, pp. 268-314,   and opportunities,” IBM Journal of   power-efficient, high-bandwidth
             2001.                              Research and Development, 63.6     heterogeneous integration,” IEEE
         21. M. Ishida, “APX (Advanced Package   (2019): 4-1.                      69th ECTC 2019.
             X) - advanced organic technology   30. A. Martwick, J. Drew, “Silicon   40.  Y. Zhang, X. Zhang, M. S. Bakir,
             for 2.5D interposer,” in CPMT      interposer and TSV signaling,”     “Bench ma rk i ng digit al die -
             Seminar, Latest Advances in        IEEE 65th ECTC 2015.               to-die channels in 2.5-D and
             Organic Interposers, Lake Buena,   31. S. Jangam, et al., “Latency,   3-D heterogeneous integration
             Vista, FL, USA, May 27-30, 2014.   bandwidth and power benefits of    platforms,” IEEE Trans. on Electron
         22.  K. Oi,  S.  Otake, N. Shimizu,    the superchips integration scheme,”   Devices   65.12 (2018): 5460-5467.
             S. Watanabe, Y. Kunimoto, T.       IEEE 67th ECTC 2017.            41.  K. Mohan, et al., “Demonstration
             Kurihara, et al.,“Development   32.  W.  J.  Turner,  et  al.,  “Ground-  of patternable all-Cu compliant
             of new 2.5D package with novel     referenced  signaling  for  intra-  interconnections with enhanced
             integrated organic interposer      chip and short-reach chip-to-chip   manufacturability in chip-to-
             substrate with ultra-fine wiring   interconnects,” IEEE Custom        substrate applications,” IEEE 68th
             and high-density bumps,” IEEE      Integrated Circuits Conf. (CICC),   ECTC  2018.
             64th ECTC, Lake Buena, Vista,      San Diego, CA, 2018, pp. 1-8, doi:   42 . C . A lva r e z , S . S u r e s h , M .
             FL, USA, pp. 348-353, May 27–30,   10.1109/CICC.2018.8357077.         Swaminathan, R. Tummala, D.
             2014.                           33. C-T. Wang, et al., “Signal integrity   Sasaki , K. Watanabe, et al.,
         23. T. Meyer, G. Ofner, S. Bradl, M.   of sub-micron InFO heterogeneous   “Design and demonstration of
             Brunnbauer, R. Hagen, “Embedded    integration for high-performance   single and coupled embedded
             wafer-level ball grid array (eWLB),”   computing applications,” IEEE 69th   toroidal inductors for 48V to 1V
             IEEE 10th ECTC (pp. 994-998),      ECTC 2019.                         integrated voltage regulators,”
             Dec. 2008.                      34. J. Kim, Y. Kim, “HBM: memory      IEEE 70th ECTC 2020.
         24. C-F. Tseng, et al., “InFO (wafer-level   solution for bandwidth-hungry   43. M. San karasubramanian, K.
             integrated fan-out) technology,”   processors,” IEEE Hot Chips        Rad ha k r ish na n, Y. Mi n, W.
             IEEE 66th ECTC 2016.               26  Symp. (HCS),  Cuper tino,      Lambert, M. J. Hill, A. Dani, et al.,
         25. J-K. Fang, et al., “A production-  CA, 2014, pp. 1-24, doi: 10.1109/  “Magnetic inductor arrays for Intel
                                                                                                              ®
             worthy fan-out solution-ASE        HOTCHIPS.2014.7478812.             fully integrated voltage regulator
             FOCoS chip last,” IEEE 70th ECTC   35.  L. J. Bum, J. A. J. Li, D. R. M. Woo,   ( F I V R) o n 10 t h ge ne r at io n
                                                                                       ®
             2020.                              “Process development of multi-     Intel Core™ SoCs,” IEEE 70th
         26. C-T. Wang, D. Yu, “Signal and      die stacking using 20µm pitch      ECTC 2020.
             power i nteg r it y analysis on    micro bumps on large scale dies,”


                       Biographies
                         Siddharth Ravichandran is a recent PhD graduate from the School of Electrical and Computer Engineering at
                       Georgia Institute of Technology, Atlanta, GA. Email siddharth.ravichandran@outlook.com

                         Madhavan Swaminathan is John Pippin Chair in Microsystems Packaging and Director - 3D Systems
                       Packaging Research Center (PRC) Georgia Institute of Technology, Atlanta, GA.





        46   Chip Scale Review   March  •  April  •  2022   [ChipScaleReview.com]
        46
   43   44   45   46   47   48   49   50   51   52   53