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the optical IOs in the interposer where References CA, 2018, pp. 70-78, doi: 10.1109/
EPB≤1.2pJ/bit can be achieved with 14. T. Hisada, Y. Yamada, “Effect of ECTC.2018.00019.
-12
a 10 BER while supporting a data rate thermal properties of interposer 16. S. Y. Hou, et al., “Wafer-level
of 896Gb/s/lane over distances of 5cm or material on thermal performance integration of an advanced logic-
more. Another option is the use of optical of 2.5 D package,” Inter. Conf. memor y system th rough the
®
fibers providing direct connectivity between on Electronics Packaging (ICEP), s e c ond -ge ne r at ion C oWoS
interposers. The network integrated circuit IEEE, 2014. technology,” IEEE Trans. on
(NIC) and photonic integrated circuit 15. T. Braun et al., “Panel-level Electron Devices, 64.10 (2017):
(PIC) dies shown in Figure 2d (in part packaging - a view along the process 4071-4077.
1), therefore, represent essential dies that chain,” IEEE 68th Elec. Comp. and 17. C-C. Lee, CP. Hung, C. Cheung, P-F.
need to be integrated in the interposer for Tech. Conf. (ECTC), San Diego, Yang, C-L. Kao, D-L. Chen, et al.,
serialization/deserialization of data and
transmission. Optical coupling efficiency,
waveguide loss and fiber alignment
continue to be major challenges for
achieving integrated photonic solutions.

Summary
For 3D stacking, power delivery and
thermal management continue to be
major problems. Emerging nonvolatile
memory (NVM) devices such as resistive
random access memory (ReRAM) and
ferroelectric field-effect transistor (FeFET)
integrated into 3D processing-in-memory
(PIM) architectures suffer from stochastic
variations in device properties and are very
sensitive to temperature. As an example,
the inference accuracy of ReRAM can
be retained over long periods only if the
junction temperature can be maintained
below 85°C. Thermal management of
NVM devices integrated into 3D stacks,
therefore, represents a major challenge
without which PIM- or HMC-based
architectures may not be viable. Embedded
fluidic channels in the stack for cooling
these devices are therefore critical, which
is an ongoing research area in academia.
To summarize, a combination of 2D
packaging and 3D stacking are required
for supporting current and emerging AI
applications. With Moore’s Law slowing
down, advanced packaging is the path
forward for continuing it at least for the next
decade. The capability of interposers has
advanced significantly in the last few years
and this trend needs to continue. Advanced
interposers of tomorrow will need to
support digital, RF and optical functionality
combined with high energy efficiency, low
latency, and high bandwidth density—three
metrics that will drive the next-generation
of packaging technologies. Though HBM
has become prevalent, 3D stacking of logic
and memory continue to pose problems
because of thermal management, and unless
embedded cooling methods are developed
inside the 3D stack, they will continue to
pose problems.

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