Page 44 - Chip Scale Review_March April_2022-digital

150x lower RC and a 12.5x lower IR from the environment is necessary; and 2) the IO count and routing on a single layer.
drop when compared to micro-bumps over shorter distances for energy-efficient Lowering the number of layers is critical
[35]. However, hybrid bonding requires computing. The best mode for interaction to reducing package thickness, improving
stringent surface planarity and usage of with the environment is through wireless overall yield, and lowering warpage.
advanced cleanrooms, thereby limiting using emerging technologies such as The other key parameter is assembly
the potential use of this technology in 5G (24GHz–100GHz) and beyond (6G pitch. Solder-based assembly is now
a package foundry. The bump pitches over 100GHz) to support the bandwidths reaching fundamental limits in pitch scaling
today are <10µm, and with improved required. Using these technologies requires as dimensions reduce below 30µm. With
tools and alignment techniques, the integration of RF dies (GaAs, InP, power emerging applications requiring current
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pitch can be further scaled down to amplifiers, and Si beam formers) along handling capability exceeding 10 A/cm ,
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1µm and below [38]. Hybrid bonding with front-end circuity such as antenna operating temperatures above 85°C, and
not only eliminates the need for bumps, arrays, passive elements such as matching thermomechanical reliability at small
but also reduces the pad sizes, thereby networks, power dividers, diplexers and stand-off heights, new technologies are
sig n if ica ntly i mprovi ng energ y- others, along with embedded and assembled required. One approach is hybrid bonding
efficiency (as shown in Table 3). dies in the interposer, as shown in Figure 2d for scaling IO pitch to <1µm. However,
(in Part 1). The heat flux for these dies varies this process is foundry-limited and current
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2
Non-TSV based 3D between 0.2W/mm for 5G to 2W/mm options for high-throughput <20µm-pitches
Figure 6f shows a non-TSV 3D for 6G, making the thermal management compatible with advanced packaging hasn’t
architecture [39] using packaging solutions quite challenging especially when progressed much. Cu-to-Cu assembly using
technologies as opposed to foundry-only the heat needs to be removed from the thermocompression bonding in a package
methods for creating 3D stacks. This back side of the die through the package foundry is a key enabler that can replace
architecture allows dies from multiple substrate. Such heat removal capabilities solder, provided reliability through improved
foundries to be connected, thereby require new thermal interface materials with compliance and higher-throughput can be
enabling true heterogeneity. Such an high thermal conductivity, and low CTE for achieved [41].
architecture does not need TSVs in the reducing stresses. The EPB in interposers can be further
logic die to establish short interconnect The interposer described in Figure 2d reduced by decreasing interconnect length
lengths and therefore can improve signal (in part 1) consists of HBM, CPU, GPU, using a combination of fine-pitch assembly
integrity, reduce real estate in expensive HMC and PIM accelerators. The CPU and and reduced L/S. For example, an assembly
dies, and decreases overall system cost. As GPU communicating with the 3D stack pitch of 10µm with L/S of 1/1µm can reduce
shown in Figure 6f, the solution consists (HBM and HMC) support near-memory length by 75% and improve interconnect
of multiple embedded dies and assembled processing, while the processor in memory density by 120% as compared to a 55µm
dies connected using RDL. There is no accelerators is added to further improve pitch and L/S of 2/2µm. Because wire
assembly required for the embedded dies. efficiency. Because the energy per bit lengths are reduced, such scaling can
In research, the IO pitch today for such a is directly proportional to capacitance, significantly decrease latency, increase
package is at 20µm with 2/2μm for L/S and achieving high energy efficiency requires bandwidth density, and improve signal
three metal layers. Unlike 2D approaches, the use of ultra-low dielectric constant integrity—all important metrics that are
because 3D solutions have area connections materials in the interposer. As described desired for emerging AI solutions.
between two dies, we compare the three in [27], a reduction in dielectric constant The platform voltage (VR) on the PWB
3D approaches in Table 3 separately, based (D k ) from 3.9 to 2.4, can reduce the EPB supports voltage conversion ratios of 48/12
on the metrics described earlier [40,37,39]. by 40% for the silicon interposer with an and 12/1 for data center applications. The
interconnect length of 5mm. Along with low large currents from the VR powering the
Future needs D k , the ideal dielectric material to maximize CPUs create routing losses, and because
As applications emerge in AI, there is a reliability should support a thickness ≤5μm, of their square law dependence on current,
need for continuous interaction and learning with moisture absorption<0.1%, tensile they reduce the overall system efficiency.
from the environment. This requires neuro- modulus <2GPa, tensile strength >100MPa, To achieve power efficiencies of 90% and
evolution in hardware, where inferences residual stress <10MPa, elongation >30%, above, integrated voltage regulators (IVRs)
need to be supported in the absence of pre- CTE<50ppm/°C, and contain no fillers. are required. The IVR needs to reside on
trained deep neural networks (DNNs) and Such materials are unavailable today, and the interposer near other dies, as shown in
labeled data sets, where energy and latency therefore, materials that meet most of these Figure 2d (in part 1). Because the interposer
are of paramount importance. For such properties are required. It is important to needs to support dies from multiple process
emerging applications a requirement is to note that a low D k combined with a thicker nodes with different voltages, several power
evolve the DNN topology continuously dielectric helps improve the efficiency of domains are required. Power management
in response to rewards using evolutionary integrated antennas provided the dissipation for AI, therefore, requires integration of
algorithms. For such architectures, data factor can be kept low (D f <0.01@ sub-THz). several IVRs on the interposer in the form
movement with low energy per bit (EPB) To scale the interconnect density beyond of buck regulator dies using advanced GaN
and high-bandwidth density become even 500 IO/mm/layer, it is important to achieve devices [42]. In addition, low dropout (LDO)
more critical. As shown in Figure 7, data a reduction in the L/S value so that it is regulators integrated into the CPU are
movement can be separated into two major less than 1µm along with reducing the required for providing fine-grained power
parts, namely: 1) over longer distances microvia and pad diameters. From [1] in management. Because buck regulators
where interaction and data collection part 1, lowering pad diameter D increases require storage devices, inductors and

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42 Chip Scale Review March • April • 2022 [ChipScaleReview.com]