Page 40 - Chip Scale Review_March April_2022-digital

2
and conductor using photolithographic a way to further scale IO count beyond towards 100x100mm and beyond, glass
processes. While these processes are assembly limits. Because these interposers interposers can become an ideal candidate
well-known, their use in advanced HDI do not have chip-level bumps, they do not provided the throughput of through-glass
packaging is limited because of two main suffer from electrical parasitics arising via (TGV) drilling and thin-glass handling
challenges: 1) Large total thickness variation from solder-based interconnects. This can in manufacturing lines can be improved.
(TTV) leading to nonplanar surfaces; and result in improved signal integrity (SI) and In Table 2 we provide a comparison
2) Dimensional instability due to a decrease better power delivery to the dies [26]. As between the various 2D approaches
in elastic modulus with temperature. we move to finer IO pitches, an important considered based on the metrics discussed
Nevertheless, there is a continuous push consideration for the selection of process earlier [30,8,31,32,33,29]. In the table we
towards advancing the scope of laminates in technology is the testability for known- also include silicon interconnect fabric
advanced packaging for cost reasons, which good-die (KGD). Yield and cycle time are (silicon IF), an approach being developed
has led to significant advances in materials also important differentiators for both these where dies are assembled onto a 300mm
for core and dielectric, along with process technologies. While in chip-last packages, silicon wafer with RDL layers, where the
advances in micro-via technology, and the KGDs are assembled after substrate wafer forms the system akin to wafer-scale
lithography. The most advanced BT-epoxy manufacturing and therefore enable testing. integration [31]. The dielectric constant
laminate core today has a CTE of 3ppm/ In chip-first packages, however, the dies (D k ) shown in the table corresponds
K, a T g of 300°C, and an elastic modulus of are committed to the package prior to to the dielectric material used for the
34GPa measured at 25°C [19]. The assembly interconnect formation and therefore, “lost” interconnections and does not represent
bump pitch today is as low as 80µm in in the event of wiring yield loss. Today, that of the core material. For example, in
production and <55µm in research and chip-last packages support 2/2µm L/S using silicon-based approaches, the dielectric
development [20,21]. The smallest line, via 3-4 wiring layers and 40µm assembly pitch, used is SiO 2 with a D k of 3.9. Apart from
and capture pad reported to date by Shinko while chip-first packages are at 5/5µm L/S lowering the standalone interconnect loss,
are 2µm line width, 10µm via diameter with with 3 layers and 80µm IO pitch [27]. a lower dielectric constant can also help
a 25µm capture pad, leading to a wiring reduce channel-to-channel crosstalk. In
density of 145 IO/mm/layer [22]. Glass-based approach chip-first fan-out, [31] shows superior
In wafer-level fan-out (WFO), or fan-out Glass has been in consideration as a core bandwidth density because of the lower
packages, the redistribution wiring and IOs material for interposer substrates because dielectric constant of the material.
extend outside of the die footprint onto the of the following advantages [28,29]: 1) 3D architectures. 3D stacking, is one
molded fan-out region where the packages glass is available in large panels (used of the best approaches for achieving ultra-
are balled for assembly. Infineon was the in displays like organic laminate panels high die-to-die bandwidth because the
first company to introduce WFO packages today) unlike the wafer forms of silicon; transistors are in close proximity to each
for radio frequency (RF) and analog 2) glass is a low-loss, insulating material other. While such approaches support
applications [23]. The first high-volume compared to CMOS-grade silicon, which short interconnect lengths, they are often
production of embedded fan-out packages is a lossy semiconducting material; 3) times limited by: 1) area occupied by
(WFO) occurred when TSMC manufactured the ultra-smooth surface of glass – like a TSVs because they are much larger than
these for the Apple iPhone 7 in 2016, using silicon wafer – is ideal for fine-pitch, high- the transistors; 2) challenges associated
integrated fan-out (InFO) technology [24]. density RDL fabrication processes using with power delivery through multiple
Although fan-out packaging has only been photolithography and planarization; and stacks; and 3) poor thermal dissipation
applied to mobile applications today with 4) glass has good dimensional stability for dies at the bottom of the stack. There
2
a die size of 13x13mm and an assembly with a high Young’s modulus of 70GPa have also been a few non-TSV based 3D
pitch of 80µm, several fan-out packages like silicon (120GPa) and, therefore, shows approaches as an alternative to foundry-
are being developed for larger ICs with a lower warpage as compared to organic only 3D stacking options. While these
<40µm assembly pitch tailored for high- laminate substrates (that have a modulus solutions address the drawbacks of TSVs,
performance computing (HPC) applications. between 20–35GPa). The CTE of glass they are often limited by the number of
Based on the manufacturing process flow, can be tailored between 3–10ppm/K. This dies connected in 3D form and therefore, a
they can be grouped into chip-first and chip- property, combined with the high Young’s hybrid combination of 2D and 3D solutions
last fan-out approaches. modulus of glass, is ideal for direct is necessary for scaling the performance of
In chip-first fan-out packages [25], assembly of a glass interposer to a PWB. a system.
dies are reconstituted into 300mm round This is shown in Figure 6e, which uses a
wafers and molded with epoxy-based glass CTE of 7–9ppm/K. This packaging TSV-based 3D
molding compounds before fabricating architecture of a 2.5D glass interposer Because 3D stacking is largely a
the RDL on these molded wafers. On the that is also the BGA package module semiconductor foundry-based process,
other hand, in chip-last fan-out packages, (the package substrate can be removed), it requires a combination of many
the RDL is fabricated on a temporary can be directly assembled onto a PWB, key technologies. First of all, TSVs
carrier upon which the ICs are assembled mitigating the parasitics arising from are formed in the dies typically using
and then molded. The fan-out module is bulky BGA organic packages. In research, the Bosch process, where the barrier
then released from the carrier for package glass interposers have been demonstrated layers are insulated and metallized.
substrate attachment. Chip-first packages with 2/2µm L/S with 4-8 layers of The second key technology is in wafer
enable ultra-thin form factors, avoid the wiring, 40µm assembly pitch and 800µm thinning (die thickness <100µm) that
need for chip-level assembly, and provide BGA pitch. As interposer sizes grow enables die stacking with reasonable

38 Chip Scale Review March • April • 2022 [ChipScaleReview.com]
38