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Thermal interface materials
                                                                              requirements
                                                                                As a basic overview, thermal engineers
                                                                              are looking for a single choice of thermal
                                                                              interface material that can:

                                                                                •  Be applied in a simple process at
                                                                                  room temperature with minimal
                                                                                  capital expenditure;
                                                                                •  Give a consistent result over
                                                                                  increasingly dissimilar die heights
                                                                                  and heterogeneous surfaces subject
                                                                                  to warpage and height differences;
                                                                                •  Reliably remove heat at high heat
                                                                                  densities;
                                                                                •  Be applied to bare silicon die (without
                                                                                  requiring die backside metallization)
                                                                                  with no reliability issues; and
                                                                                •  Be applied over multiple larger die
        Figure 3: Some of the 3D challenges for HPC modules.
                                                                                  with significantly larger surface area.
        thermal conductivity of silicon itself   issues in compute intensity, multi-die
        (around 1.4W/cm.K at room temperature)   integration, and other factors of increasing   Bulk thermal conductivity and
        can become a performance impediment.  relevance to HPC modules and systems.   thermal resistance
          The complications of HPC modules are   One critical factor in HPC module thermal   When considering a potential TIM
        already well-delineated in industry roadmap   and packaging design is the selection of the   solution, the key performance metric
        workshops, such as those from IEEE [6] and   materials used to gain the most efficient heat   is the overall thermal resistance (units
        iNEMI. These roadmaps outline emerging   transfer, internally and externally.  K/W). Bulk thermal conductivity is
                                                                              usually an important consideration for
                                                                              thicker bondlines, but as the bondline
                                                                              thick ness of the TI M decreases,
                                                                              interfacial resistances dominate the
                                                                              system’s thermal performance (Figure 4).



















                                                                              Figure 4: Diagram of heat flow.


                                                                              Generalized TIM types
                                                                                There are three general types of TIM,
                                                                              each relevant to the semiconductor package
                                                                              design and the packaging level where the
                                                                              TIM is to be applied as noted below.
                                                                                TIM 0. In these applications, which are
                                                                              increasingly being used in HPC modules,
                                                                              the  TIM0  contacts  the  die  backside
                   E-Tec Interconnect  AG, Mr. Pablo Rodriguez,  Lengnau Switzerland
                       Phone : +41 32 654 15 50, E-mail: p.rodriguez@e-tec.com  surface and transfers heat directly to the
                                                                              heat sink base (Figure 5). This is usually
                                                                              a machined copper surface compressed


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