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chiplet pairing does not have a clear one- how does one adequately characterize assembly. But much more innovation is
size-fits-all answer and depends on the a chiplet when not all the metal layers needed in the DFT space to ease testing
desired outcome, which can change based have been completed and the power and enable resilient, self-healing designs.
on the product being assembled as well as delivery network is not identical to the An immediate area of focus should
customer demand fluctuations throughout final metal stack? And second, how does be better I/O DFT that provides better
the life of the product. Combining the one guarantee KGD in an open loop flow coverage at wafer test and reduces the
die in a purely random fashion would where there is additional processing after stack test, shown in Figure 4, to a simple
create a higher concern for meeting the wafer test, but prior to assembly? assembly health monitor test (AHMT).
minimum frequency of operation while The brute force approach of adding The test industry will also need to
helping control the total power of a unit. more complexity to test hardware and deliver innovations in support of driving
On the other hand, combining chiplets test content is destined to bend the cost down cost. Probe card suppliers will
with the same characteristics will result curve in the wrong direction and lead need to invest in new manufacturing
in the best result for minimum frequency to test becoming a limiter to Moore’s techniques, such as fab-like build-
of operation, but would result in higher Law. Instead, to overcome some of up processes, to expand their capacity
overall power for a unit. Having a well these challenges, test will need to rely while driving down cost. Automated
characterized chiplet enables intelligent more on artificial intelligence (AI) and test equipment (ATE) suppliers will
pairing to achieve the desired outcome. take advantage of big data analytics to need to deliver low- cost, mega-
Characterizing chiplets at wafer level, drive faster yield learning, optimize test parallel, asynchronous test solutions to
however, is not trivial and requires better content on a per unit basis, and better compensate for the added sockets in the
and more standardized test hardware, predict the characteristics of a device flow. Assembly equipment suppliers need
along with more test content, which based on the wealth of fab and test data to consider integrating fast and low-cost
result in higher test cost. For example, available. This will require companies AHMT capability within their tools for
subtle differences in the power delivery to invest in AI infrastructure and faster process feedback.
network of a probe card from two test engineers will need to be trained
different suppliers can have a significant on developing better AI algorithms. Summary
impact on the measured frequency of a Companies will also need to invest in It is often said that these are exciting
device. In a world where chiplets come hardware and automation infrastructure times to be a packaging engineer as
from different nodes and different to deal with the complexity associated advanced packaging is the next frontier
foundries, that are tested on different with intelligent pairing of die. For along the continuum of Moore’s Law. It
test platforms, using different probe card example, assembly tools will need to is equally exciting to be a test engineer
technologies from different suppliers, support complex asynchronous pick-and- as future challenges provide boundless
it will become increasingly difficult place algorithms and management of opportunities to innovate. There is,
and expensive to properly characterize multiple sub-populations to achieve the however, little margin for error. Test cost
chiplets for pairing decisions. desired results. per transistor used to be several orders
There is also a need for stronger of magnitude smaller than transistor
The future of test collaboration between design, packaging, manufacturing cost. Today, that gap has
A looming problem on the horizon is and test to ensure solutions are optimized narrowed and if test engineers and the test
the insatiable appetite for interconnect for cost. Such collaborations took place industry are not able to keep pace with
density by the design community, two decades ago where addition of self- transistor manufacturing costs, then test
which is driving the pitch roadmap into test modes enabled the transition to lower will become a limiter to Moore’s Law.
regimes where traditional solder bump cost structural test platforms. Today, Our goal here was to bring awareness
interconnects are no longer feasible. design teams have recognized that it will to these challenges just as the ITRS
This will force the industry into using be easy to make chiplets that work in roadmap did more than twenty years ago.
hybrid bonding to connect chiplets isolation but are not economically viable We invite test technologists across the
together, which will severely challenge because of complex manufacturing industry to propose bold and innovative
test. Putting aside the technical and flows and the inability to fully test solutions to take on these challenges.
economic viability of building probe the chiplets until they are integrated.
cards at <10μm pitch, the fundamental Efforts are underway to address some References
problem is how to test these wafers prior of these challenges through interface 1. G. E. Moore, “Cramming more
to chiplet integration. Hybrid bonding standardization that would enable better components onto i nteg rated
requires pristine bond pads that are access points for test pre- and post- circuits,” Electronics, 1965, Vol. 38.
sensitive to defects as small as 10nm. assembly. In addition, standards are 2. International Technology Roadmap
Probing these pads will create divots and needed for a minimum feature set on for Semiconductors: Test and Test
pile-up that are considered killer defects. chiplets to ensure basic connectivity, Equipment, p.11, 2001 Edition.
Some have proposed testing the wafers power delivery, and functionality at 3. B. Holt, “Moore’s Law, 40 years and
prior to building the hybrid bonding wafer level. Other approaches include counting: Future directions of silicon
layers, while another option is to send built-in redundancy of cores and IP and packaging,” InterPACK, 2005.
the wafers back to the fab to re-polish blocks, and enabling end-of-line repair/ 4. TM Mak, “Microbumps – to
and repair the probe marks [11]. These configurability to account for noise, probe or not?,” Test Vision 20/20,
solutions pose multiple problems. First, power, and thermal variations post- SEMICON West, San Francisco,
2014.

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