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frame-based packaging, and the use of an overload. Instead of dissipating the heat
integrated half-bridge. These topics are to the bottom and into the PCB, it could
discussed below. also be done the other way round, i.e.,
Face-down chip assembly enables two dissipate the heat to the top (Figure 4).
major improvements compared to wire With leaded packages, this would mean
bonded solutions: 1) optimized/smallest a simple reverse bending of the leads.
package footprint, and 2) the shortest Leaded packages such as, system on
interconnect technology (Figure 1). integrated circuit (SoIC™), or quad flat
The biggest challenge of flip-chip attach package (QFP), typically come with
packages is the limited reliability on the a standoff (i.e., the distance between
printed circuit board (PCB). Because the bottom surface of the package and
the bottom surface of the leads) of up
Figure 2: An EPS system diagram [2]. to 200µm.The tolerance is related to
the bending process of the leads. The
can the board space be optimized, but tolerance of the overall package height,
stray inductance and minimized switching including the package body and the
losses with advanced electromagnetic standoff, can add up to about 300µm.
interference (EMI) performance could If one also considers tolerances from
also be realized (Figure 3). the board mounting process (solder
Increased heat dissipation. To thickness, PCB flatness, housing, etc.)
manage increasing power densities, and this can easily add up to 500µm and
thereby the resulting heat dissipation, more. In a topside cooling application,
the heat input into the PCB must the thermal interface material (TIM)
be reconsidered to avoid a thermal must compensate for this tolerance
build-up to ensure a proper
contact between the topside
Figure 1: Package shrink-wire bond versus flip chip. of the package to the cooling
a r e a ( F i g u r e 5 ) . A s a
the chip is soldered face-down on the consequence, using a thicker
substrate, copper pillars need to buffer TIM increases the thermal
the stress from the coefficient of thermal resistance of the thermal
extension (CTE) mismatch between the path between the topside of
Si/chip (~3ppm/K) and the laminate/PCB the package and the cooling
(~16ppm/K). An intensive design study area, thereby reducing the
was performed and improvements with thermal performance of the
respect to bump design, bump layout on application.
chip, and process optimizations were One way to minimize the
implemented. The results of the study package height tolerances
showed that the temperature cycle on is by way of a so-called
board (TCoB) performance allows usage negative standoff (Figure
in automotive applications, even in a 6). In this case, no lead will
high-temperature environment (e.g., an extend the bottom surface
ambient temperature of 150°C). Figure 3: nfineon’s integrated half-bridge in a TDSON8 package of the package. The whole
The second topic with respect to (IP generated). package height tolerance is
miniaturization is use of an integrated determined by the package
half-bridge. Electrical power steering body height. With this topside
(EPS) functionality as a safety-critical cooling TOLT package, a
application must be guaranteed under 20% reduced Rth compared
all circumstances. For autonomous to bottomside cooling can be
driving, this would mean that such realized (Figure 7).
an application needs to be redundant
to ensure safe operation, even if one eMobility
component is failing. T he t h ree megat rends
Having system redundancy simply we have been discussing
means to double up the system. Figure 2 make different contributions
shows an EPS system in which the bridge with respect to reliability
consists of 6 MOSFETs. The redundant requirements, yet they all
system would also be built with 6 result in a movement in the
MOSFETs, so, 12 MOSFETs in total. With same direction. There is an
an integrated half-bridge solution, not only overall clear visible trend
Figure 4: Top side cooling (TSC).
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