Page 19 - Chip Scale Review_July August_2023-digital

o Static timing analysis (STA) with
automated corner reduction; and
o Rule-deck-free SystemLVS for
3D package-level alignment and
connectivity checking.
• Comprehensive thermal stress and
design for manufacturability (DFM)
tools for chemical mechanical
polishing (CMP) planarity checks
across the dies.

These tools should allow the designer
to aggregate the chiplets and packaging
technologies to plan and optimize the top-
level design. Apart from this, the tools should
have the ability to work at very abstract levels
of the design to make designers capable of
performing early-stage analysis of the 3DHI.
Additionally, next-generation design
flows need to move more analysis further
upstream in the design process. EDA
technologists have used the term “shift-left”
to describe moving electrical analysis into
the layout tools, but for 3DHI, the analysis
tools need to be shifted further left into the
design planning stage. Thermal analysis,
for example, must be performed as early as
possible when considering stacking silicon.

Summary
As we advance with 3DHI, design
methodologies are becoming even more
complex. Companies willing to invest in their
design flows will have a competitive edge.
As the domains of die and system design
converge, many new challenges await ASIC
and package designers entering the world of
“Moore-than-Moore.” An integrated design
methodology across IC, package, and board
design, along with analysis and verification
moved further upstream in the flow, will
be vital in enabling designers to focus on
design work, not design tools. Seamless
integration across the tools will significantly
reduce design cycle times and enable co-
design and co-analysis across IC, package,
and PCB domains.

Biographies
John Park is Product Management Group Director for Advanced Semiconductor Packaging at Cadence
Design Systems, Louisville, CO, where he leads a team responsible for defining cross-domain solutions
and methodologies for IC, package, and PCB co-design and analysis. His team is especially focused on
developing tools and flows for chiplet-based 3D designs. He has over 40 years of experience in the EDA
field and is regarded as an international expert on chiplets, packaging, and heterogeneous integration.
Email jpark@cadence.com

Vinod Kumar is Lead Marketing Communications at Cadence Design Systems, India. He received a PhD in VLSI from NIT,
Kurukshetra, India. Vinod has worked in the semiconductor industry for over 12 years in the domain of VLSI and embedded
systems design.

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