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Using a combination of chip-, package-, thermal and stress performance. So it is Test and testability
and system-level thermal modeling, very important to not wait until design The production test methodology
designers can generate power-aware of the package assemblies is complete. used in digital, homogeneous designs
thermal and stress device-level models Instead, start with predictive analysis has been established for many years:
that provide greater accuracy for thermal before or during the prototyping/ deploying structural design-for-test
and mechanical simulations (Figure 5). planning phase. Starting analysis as (DFT) logic implemented during the
The models can then be used to perform early as possible in the process allows ASIC design process. DFT test tools are
warpage, stress, and fatigue analysis. for the most flexibility in making choices run on the inserted test logic to generate
When it comes to material choices, and tradeoffs and usually results in the the ATE production test programs used
substrate stackup and device or chiplet minimum impact on the design. for wafer- and package-level production
proximity have considerable impact on testing. Additionally, boundary scan
description language (BSDL) test
patterns are generated for the design to
be used for PCB-level tests.
Heterogeneous chiplet design requires
extensive changes and additions to
the traditional, homogeneous design.
Because these designs include two
or more ASIC/chiplet components,
a production test program must be
provided for each of the inter nal
c omp one nt s. It i s a s s u me d t h at
externally-sourced chiplets will be
wafer-sorted and delivered as a known-
good-die but will still need to be retested
once they are assembled in the system-
in-package (SiP) device. Furthermore,
these tests need to be run from the
external package pins, most of which
are not connected directly to the chiplet
pins. In addition to the individual die
testing, the interfaces between each
component need to be functionally
tested, preferably at speed for each of the
die-to-die interfaces.
IEEE test standards are being developed
to accommodate these 2.5D test methods.
Different tool vendors may deploy
different approaches in implementing
these standards, which may cause test
compatibility issues of components that
use different DFT vendor tools. For
board-level testing, a composite BSDL
file for each of the internal components is
preferred, but not necessarily supported,
by all DFT tool vendors, which further
complicates the PCB-level testing.
W i t h t h e i n t r o d u c t i o n o f 3D
heterogeneous designs, additional
challenges are introduced as the die
stacked above the base die may not be
accessible through traditional BSDL/
JTAG interfaces. There are additional
emerging IEEE test standards being
developed to accommodate 3D test
methods as well (Figure 6). These
methods deploy hierarchical test methods
that can only test the stacked die after
assembly. Just as with 2.5D, DFT vendor
capability issues will likely arise in 3D
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40 Chip Scale Review May • June • 2023 [ChipScaleReview.com]
