Page 9 - Chip Scale Review_January February_2023-digital

complex array of packaging technologies Tan, Nanyang Technological University
that lie under the hood of such devices, (Singapore).
spanning the three areas of augmented reality A highlight of the conference was the
processing (ARP), display and imaging banquet (Figure 6), which was held on Mount
(D&I) and low-energy wireless (LW) Faber, from which delegates were able to enjoy
communication. Meta has demonstrated a spectacular view of the southern coastline.
unique approaches that combine advanced
packaging technologies like flip chip, fan- Figure 5: Panel on “Chiplets as an Enabler for
out wafer-level packaging and through- System Scaling.”
silicon via (TSV)—often within the same
package. He discussed the challenges created The panel revisited the drivers behind chiplets
by the need to spawn new ecosystems, technology, the manufacturing ecosystem, and
such as heterogeneous integration and use cases. The Universal Chiplet Interconnect
®
fabrication methods that often fall in the Express (UCIe ) was also discussed. The
grey zone between foundry and outsourced panel ended with a critical examination of the
semiconductor and test (OSAT). supply chain and market outlook. Figure 6: Conference banquet at the Mount Faber
Dr. Sundar Ramamurthy, VP & GM The HIR workshop was held at the Restaurant.
Advanced Packaging, Applied Materials, end of the conference with the theme:
delivered the third keynote entitled, “Materials “Heterogeneous Integration Paving the The delegates had a great networking session
Engineering Innovations to Address Next- Way for Global Electronics Resurgence.” after more than two years of not being able to
Gen Electronics Packaging Challenges Heterogeneous integration through do so in person because of COVID-19.
(Figure 4).” He declared that hybrid bonding advanced packaging innovations is widely The EPTC2022 Executive Committee
needs new dielectrics and optimized copper acknowledged as being increasingly would like to thank all our conference
important to drive performance, system delegates, sponsors, exhibitors, partners and
availability, power efficiency, cost and time all other contributors for their participation.
to market of microelectronics systems— Industry partners have continued their strong
from high-performance computing (HPC) support of the EPTC in 2022, which has
and data centers, to 5G and beyond, mobile, enabled EPTC to be an excellent platform
autonomous automotive, IoT, and the medical for packaging technologists from all over the
and health markets. The HIR is a system- world, but especially from Asia, to share and
and application-driven roadmap inclusive exchange information and ideas on electronics
of the full microelectronics technology packaging technologies. Special thanks to
Figure 4: Third keynote speaker, Dr. Sundar ecosystem with the purpose of delivering the the Organizing Committee (Figure 7) for its
Ramamurthy, Applied Materials. next extension of Moore’s Law for decades strong commitment, dedication and support
to come. Dr. Ravi Mahajan gave an overview in making EPTC2022 a memorable event!
grain morphology that enable low-temperature of HIR that was followed by presentations
processing. Tuning chemical mechanical on: 1) the supply chain by Dr. Kitty Pearsall,
processing (CMP) for optimal bond surface EPS President; 2) thermal management by
profiles can improve the efficiency of the Dr. Gamal Refai-Ahmed, AMD; 3) 2D–3D
bonding process. Panel-level packaging offers Interconnects by Dr. Ravi Mahajan, Intel; and
the ability to reduce cost by moving to a larger 4) updates on photonics by Prof. Amr Helmy,
format, but new challenges for handling large University of Toronto.
substrates need to be overcome. Speeding A Packaging Education workshop was
up yield learning and addressing defect organized by Profs. Jeff Suhling and Andrew Figure 7: EPTC2022 Organizing Committee.
sources also require increased inspection and Tay. The main objective of the workshop
monitoring for known-good die. Materials was to discover what some universities in EPTC2023 will be the 25th Anniversary
challenges and engineering innovations that Asia are doing to prepare their students to of EPTC and will be held in the Marina
are enabling the advances required for the enter the electronics packaging industry. The Bay Sands Convention Centre, Singapore,
next generation of electronics packaging were following professors shared specialization on Dec. 5-8, 2023. The normal 3-day
also shared. programs on electronics packaging in their conference will be extended by a day for an
Following the keynotes was a panel session respective universities and countries: 1) Prof. extra-special program of celebration. The
on “Chiplets as an Enabler for System K. N. Chiang, National Tsing Hua University fall meeting of the EPS Board of Governors
Scaling,” which was moderated by Prof. CS (Taiwan); 2) Prof. Wenhui Zhu, Central (BoG) will be held in conjunction with
Tan (Figure 5). The panel speakers were Dr. South University (China); 3) Prof. Gu-Sung EPTC2023 and many of the BoG members
Ravi Mahajan, Intel; Dr. Raj Pendse, Meta Kim, Kangnam University (South Korea); are expected to play a role in the conference.
Reality Labs; Dr. Bernd Dielacher, EVG 4) Prof. Anandaroop Bhattacharya, IIT The Call for Papers will be posted soon at
Group; and Dr. Yik Yee Tan, Yole Group. Kharagpur (India); and 5) Prof. Chuan Seng https://www.eptc-ieee.net/.

Chip Scale Review January • February • 2023 [ChipScaleReview.com] 7 7