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of the mechanical protection layer a s s e m b l y a n d i n ter c o n n ec t i o n ne e d for va cuu m-ba se d br a z i ng
b e t we e n t h e si nt e r e d l aye r a n d technologies. Various metal ceramic tech nolog y. T he tech nolog y ha s
the die, then propagating into the substrates have been used; however, been proven by thermal shock, peel
front-side metallization of the die. each provides drawbacks, including st reng th, ther mal measu rements
A degradation of the die attach is precious metal content and a slow and thermal simulations. Numerous
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also observed. In the case of direct vacuum brazing process. We have studies show that Condura .ultra
cooling, the same break propagation found a solution that offers a cost- enables cost-efficient, but highly-
f rom the edge of the mechanical eff icient, highly-reliable Ag-free reliable met al ceramic subst rate
protection layer down to the front- thick-f il m copper bonding paste manufacturing using Ag-free paste
side met a l l i z at ion of t he d ie is that joins nitride-based ceramics and a non-vacuum-based brazing
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also obser ved. However, t here’s with Cu foils and eliminates the process. Additionally, DTS can
no degradation of the die attach,
probably due to the more efficient
heat d issipat ion. Fi n ite element
model (FEM) analyses show that
t he l ifet i me reduct ion m ig ht be
r el a t e d t o a n i n c r e a s e d pl a s t ic
s t r a i n p e r c ycle i nt o t he f r ont-
side metallization of the die. This
could be due to a higher stiffness
of the test vehicle and /or to the
temperature being locally higher on
the die at higher currents [6].
B y e n a b l i n g h i g h e r p o w e r
d e n s it ie s a n d h ig h e r o p e r a t i n g
t e m p er a t u r e s , o u r m ec h a n i c a l
p r o t e c t i o n l a y e r t u r n s o u t t o
b e a s u i t a b l e s o l u t i o n f o r t h e
i nt e r c o n n e c t io n s of SiC m e t a l-
oxide semiconductor f ield-effect
t r a n s i s t o r s ( S i C -M O S F E TS ) .
Power cycling tests demonstrated
a doubli ng of t he lifet i me when
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using DTS compared to sintered
dies with Al interconnections [8].
More recently, power cycling tests
up to 20 0°C have been repor ted
w it h D T S a n d a 1, 20 0 V S i C -
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MOSFET from Wolfspeed [9]. In
this case, the failure mechanism
is a cohesive break in the sintered
l a y e r, a l t hou g h a b r e a k i n t h e
f r on t- s i d e m e t a l l i z at ion of t h e
d ie wa s expected. However, t he
number of cycles to failure is in
line with results reported at lower
o p er a t i n g te m p er a t u r e s , t h er e -
by demonst rating the robust ness
of both die and package at 200°C
(Figure 13).

Summary
As the semiconductor indust r y
c o n t i n u e s s e e i ng h i g h - p o w e r
electronics applications, there is
a need to provide reliable met al
ceramic substrates that offer superior
electrical, thermal, insulation and
mechanical performance while also
bei ng able to work w it h t y pical

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