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High-precision die attach: a major pillar of advanced packaging

By Percy Lam [ASMPT Limited]

O v e r t h e l a s t d e c a d e , The continued node development Important requirements for die

semiconductor technology
node advancement and from 10nm down to 2nm and even attach tools
smaller is in question, however,
In order to actualize the intended
the gradual increasing sophistication of as the commercial returns are not advanced package structure, specifying
advanced packaging have happened in commensurate with the extremely high adequate and realistic requirements for
tandem. Commencing with the introduction capital investment required. In order die attach tools during the tool selection
of embedded wafer-level ball grid array to reduce the financial commitment for process is a vital aspect of a quality-first
(eWLB) technology by Infineon more than future node development, an effective execution strategy. The following sections
10 years ago, followed by the introduction of approach is switching from “only front- discuss the applicable requirements for die
2.5D packaging known as Chip on Wafer on end node scaling” to “a combination attach tools.
®
Substrate (CoWoS ) by TSMC, a growing of front-end scaling with back-end Die placement accuracy. Capability of
number of innovations in the arena of scaling.” Heterogeneous integration higher die placement accuracy depends on
advanced packaging have been contributed (HI) is the way forward (Figure 2). HI machine design of the die attach tool itself
by major manufacturers. According to Yole is an approach using AP technologies (Figure 4). Machine cost usually increases
Group’s advanced packaging market report that enable the integration of multiple with die placement accuracy and is inversely
in 2020 [1], advanced packaging revenue chiplets with different functionalities related to productivity. Figure 4 shows an
is swiftly catching up to the traditional and each fabricated using the best example of a high die placement accuracy
measurement result based on the bond mode
packaging market. In 2014, advanced fit node in terms of technology and of a face-up die where the local alignment is
packaging (AP) accounted for 38% of the economics, to reassemble a system-on- executed by a high-precision die attach tool.
total packaging market. However, its (AP) a-chip (SoC)-like function. Various bond modes. To support the
market share will increase to around 50% A nontrivial issue usually encountered three bond modes of fan-out packaging, i.e.,
in 2025, or around $42 billion. In an 11- by foundries or assembly houses using die first/face up, die first/face down or die
year period from 2014 to 2025, AP revenue AP to realize the concept of HI is the last/face down, easy switching among the
is forecast to almost catch up with that of large variety of die attach requirements different modes is a basic requirement. A
traditional packaging. needed to meet the ever-evolving AP heated bond collet tool and a heated bond
The AP development roadmap closely technologies. High-precision die attach chuck for die attach film (DAF) bonding
follows the path of the advanced node requirements have become a critical are required for die face-up bonding at
front-end roadmap provided by the three factor in accomplishing a successful AP elevated temperatures. Flux dipping for
major leaders in the world, namely TSMC, rollout (see Figure 3). mass reflow flip-chip bonding is an option
Intel and Samsung (Figure 1). for redistribution layer (RDL)-first/die-

Figure 1: Technology roadmap – front-end manufacturing vs. advanced packaging. SOURCE: Yole Group, 2020 [1]

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