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the EIC die are located directly below
the photonic IC. This is enabled by
utilizing a double-sided fan-out wafer-
level package structure that embeds
two driver EIC dies right below the
photonic IC die, thereby minimizing
the critical length between the dies.
This type of sub-module integration
can help to enable another level of
performance improvement for CPO.

Summary
Six critically important packaging
technologies form the pillars of ASE’s
VIPack™ platform and are supported
by a comprehensive and integrated
co-design ecosystem. As described
in this article, these pillars include
ASE’s high-density RDL-based FOPoP,
FOCoS, FOCoS-Bridge, and FOSiP,
as well as TSV-based 2.5D and 3D
Figure 15: Traditional routing vs. advanced RDL integration. IC and CPO processing capabilities.
The V IPack™ platfor m provides
light-based lines. Silicon photonics has IC packaging methodology. Looking the capabilities necessary to enable
been around since the mid-90s, but has at CPO closer, we see that this more highly-integrated silicon packaging
faced technical and cost challenges. integrated packaging methodology solutions required to optimize clock
Since then, technical improvements is bringing the critical components speed, bandwidth, and power delivery,
and power-hungry scaling bandwidth closer together to minimize losses and to reduce co-design time, product
requirements have driven the industry between the electro-optical conversion development, and time to market.
to accelerate the adoption of silicon process. Because of the custom nature These six pillars will help to deliver
photonics. Advances in module-based of photonics ICs, CPO generally does unique opportunities to those seeking
packaging of both pre-packaged and not follow any pre-defined packaging optimum efficiency and performance
non-packaged components have helped rules, which leads to many different for their applications. The technology
in the evolution toward CPO. When types of configurations within the pillars are built upon an open silicon
we look at the various ways network industry. To further improve the CPO e c o s y s t e m i n p a r t n e r s h i p w i t h
switches can be organized, there is area, components must be integrated in foundries, component suppliers, and
a clear reason why co-packaging the the most efficient way while keeping across the supply chain to provide
switch die and optics are key. Figure in mind the best way to attach the design flexibility required for product
14 shows the increasing insertion loss optical fiber. As mentioned above, re al i z at ion. A s p e ct r u m of new
(lower performance) and higher power when components are placed in a 2D process tools further enhances ASE’s
requirements depending on how the plane, there are longer lines and losses current toolbox of capabilities and
communication is handled between associated with the layout. This can be supports evolving package structures
the transmit and receive functions of further enhanced by creative packaging being developed in alignment with
the backplane. as shown in Figure 15. This figure industry roadmaps.
This co-package conf ig uration shows a traditional PIC die next to the
i mprovement reduces t he losses EIC, side-by side approach, but a more
between transmission lines and should efficient structure is shown by vertical
follow similar rules when looking at coupling or grading coupling where

Mark Gerber Lihong Cao Vikas Gupta Patricia Macleod
Sr. Director, Engineering Sr. Director, Engineering Sr. Director, Technology Director, Marketing &
& Technology Marketing & Technology Marketing Development, Roadmap & Strategy Communications
ASE US ASE US ASE US ASE US

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