Page 12 - Chip Scale Review_March April_2022-digital

This may be the end of solder-based 2. I . H s u , e t a l. , “ Fi n e - p i t c h technology,” IEEE Trans. On
assembly. Direct bonding of copper i ntercon nection and highly- Electron Devices, vol. 64, no. 10,
t o c op p e r h a s b e e n pu r s ue d for integrated assembly packaging pp. 4071–4077 (2017).
more than a decade using advanced with FOMIP (fan-out Mediatek 11. 3Di ncites. (2020), [Onli ne].
t he r mo c o m p r e s s i o n b o nd i n g innovation package) technology,” Available: https://www.3dincites.
technologies. While the progress has IEEE 70th Elec. Comp. and Tech. c o m /20 20 / 1 0 / i f t l e - 4 6 4 -
been outstanding, these assembly Con f. ( ECTC), pp. 867– 872 t smcs-fa m ily- of-pa ck ag i ng-
technologies tend to be slow and (2020). technologies-are-built-on-3d-
difficult for high-volume production. 3. W.- S . Kwo n , e t a l ., “ C o s t- fabric/
It is because of this reason that hybrid effective and high-performance 12. L. Li, et al., “3D SiP with organic
bond i ng be ca me a ve r y popu la r 28nm FPGA with new disruptive interposer for ASIC and memory
technology, originally invented by s i l i c o n - l e ss i n t e rc o n n e ct integration,” (2016) IEEE 66th
Ziptronix about 15 years ago, and technology (SLIT),” International ECTC, pp. 1445–1450.
currently licensed to Xperi. Both Symp. On Microelectronics, Inter. 13. T. Yamada, “Organic interposer
TSMC and Intel are pursuing this Microelectronics Assembly and and embedded substrate,” in
technology very aggressively showing Packaging Soc. (2014), pp. 000 Pa c k a g i n g S y m p., Kyo c e r a
plans for 10µm pitch in the short 599– 000 605. America, Inc., 2015.
term, and 1µm pitch within a decade. 4. JCET- “Embedded wafer-level ball 14. K. Oi, et al., “Development of
Simultaneously, tool makers like grid array technology,” (2019), new 2.5D package with novel
Applied Materials are developing the http://jcet.workspacep5.webfoss. integrated organic interposer
necessary production tools. com /uploads/eW LB%20 -%20 substrate with ultra-fine wiring
Embedded%20Wafer-Level%20 and high-density bumps,” IEEE
Summary B a l l% 2 0 G r id% 2 0A r r ay % 2 0 64th ECTC, 2014, pp. 348–353.
In summary, a historic shift from Technology%20(FOWLP).pdf 15. J. Kim, et al., “Fan-out panel-
transistor scaling to system scaling 5. C. Zwenger, R. Huemoeller, J. level package with fine-pitch
and integration has begun, leading to Kim, D. Kim, W. Do, S. Seo, pattern,” IEEE 68th ECTC, 2018,
many other shifts such as glass panel “Silicon wafer integrated fan-out pp. 52–57.
packaging, reaching 1µm lithography, technology,” Additional Papers 16. D. Okamoto, et al., “Fabrication
and IC assembly reaching 1µm pitch and Presentations, vol. 2015, no. and reliability demonstration
withi n a decade — t wo histor ical DPC, pp. 000 217–000 247 (2015). of 3μm diameter photo vias at
milestones. The current panel technology 6. J. K. Fang, M. L. Huang, H. J. Tu, 15μm pitch in thin photosensitive
is based on laminate or build-up organic W. L. Lu, P. Yang, “A production- dielectric dry film for 2.5D glass
technology, which has been known to be worthy fan-out solution-ASE interposer applications,” IEEE
incapable of 1µm lithography. In parallel, FoCoS chip last,” IEEE 70th 69th ECTC, pp. 2112–2116 (2019).
IC assembly is being advanced with ECTC, pp. 290–295 (2020).
micro-bumps to 10µm pitch in the short 7. H.-P. Pu, H. Kuo, C. Liu, C. Biographies
term, and later, towards a 1µm pitch Douglas, “A novel sub-micron Rao R. Tummala is a distinguished
using direct Cu-Cu bonding (also known polymer re-distribution layer emeritus Professor at the Georgia
as hybrid bonding) to replace solder. technology for advanced info Institute of Technology, Atlanta, GA.
packaging,” IEEE 68th ECTC, pp. Prior to that, he was an IBM Fellow
Acknowledgements 45–51 (2018). and Director of Advanced Packaging
The authors would like to thank the 8. R. Huemoeller, “Amkor’s slim Technology Lab at IBM. He received
members of the industry consortium & swift package technology,” his PhD in Materials Science and
at the 3D Systems Packaging Research A m k o r Te c h n o l o g y , S V P Engineering at the U. of Illinois. Email
Center, Georgia Institute of Technology, Advanced Package Technology rtummala@ece.gatech.edu.
Atlanta, GA, USA for their support and Develop & IP, 2015. Madhavan Swaminathan is John
technical guidance. The authors would 9. R. Mahajan, et al., “Embedded Pippin Chair in Microsystems Packaging
also like to acknowledge the material and multi-die interconnect bridge—a and Director - 3D Systems Packaging
process support from Taiyo Ink, TOK localized, high-density multi-chip Research Center (PRC) Georgia Institute
and Atotech. packaging interconnect,” IEEE of Technology, Atlanta, GA
Trans. On Components, Packaging
References and Manufacturing Tech., vol. 9,
1. h t t p s : / / w w w . a p p le. c o m / no. 10, pp. 1952–1962, 2019.
newsroom/2021/10/introducing- 10. S. Hou , et al., “Wafer-level
m1-pro-and-m1-max-the-most- i nt eg r at ion of a n a dva nc e d
powerful-chips-apple-has-ever-built/ logic-memory system through
®
the second-generation CoWoS
10 Chip Scale Review March • April • 2022 [ChipScaleReview.com]
10