Page 51 - Chip Scale Review_January February_2022-digital

FOWLP and Si-interposer for high-speed

photonics packaging

By Lim Teck Guan, Eva Wai Leong Ching, Jong Ming Ching, Loh Woon Leng, David Ho Soon Wee, Sajay B G, et al.
[Institute of Microelectronics, A*STAR (Agency for Science, Technology and Research)]
T he ever-increasing demand Dat a center OEs use ICs f rom IME is currently developing two

for higher data bandwidth
SiGe for drivers and amplifiers, and
out wafer-level packaging (FOWLP)
in the data center has led diverse technologies such as CMOS/ packaging platforms based on fan-
to the requirement of higher speed, III-V lasers. These ICs need to be and the Si-interposer to address the
smaller form factors and scalable, integrated into very small form factor EIC and PIC integration requirement.
integrated optical engines (OE). An OE system-in-packages (SiPs) to be able The first solution is based on the
comprises various electronic integrated to bring in optical signals and convert established FOWLP technology, which
circuits (EICs) and photonics ICs them into electrical signals (and vice has been demonstrated for digital
(PICs) to enable the optical/electrical versa) to be processed by switches, and radio-frequency (RF)/mmWave
(O/E) signal conversion. With the FPGAs or other application-specific applications [3] integration. The
advancement in semiconductor device ICs (ASICs). Therefore, electronic- FOWLP has good RF performance
technology, packaging and integration photonic heterogeneous integration and allows multi-chip heterogeneous
technologies are becoming the limiting enabled by advanced wafer-level integration to be well suited for this
factors to enable the OE to meet the packaging is a promising technique to high-performance OE application.
demand of the data center’s high data realize high-speed optical engines for For the Si-interposer with a high-
bandwidth requirement of more than the data center. resistivit y subst rate, it can also
800Gbps. It is, therefore, important For the best per for mance with provide very high-speed and high-
to develop a cost-effective PIC and respect to speed, the EIC is integrated bandwidth PIC and EIC integration.
EIC packaging platform to realize a directly on top of the PIC. Currently, Additionally, it can provide a sub-
high data rate OE. The integration and silicon photonics is the most promising micron alignment feature for the fiber
packaging technologies must support tech nolog y t hat ca n provide t he to the PIC passive assembly.
the scaling of the number of optical necessary performance and highest
channels and provides a high-speed functionality integration. The PIC here Photonics FOWLP
electrical interconnect between the is an active interposer—it not only The FOWLP integration platform
PIC and EIC of each channel of more consists of the photonics circuit, but also w e d e s c r i b e i s f o r h i g h - s p e e d
than 100Gbps. provides the necessary physical area PIC and EIC integration. It is low
Advanced wafer-level packaging for the EIC and external routing and c o s t a nd it le ve r a ge s a d v a n c e d
has been successfully used in state- integration [1]. However, this is a costly FOWLP development for electronic
of-the-art field-programmable gate solution because the PIC will require semiconductor packaging. Currently,
a r r a y ( F P GA) IC s , s m a r t pho n e an additional large area to support only the PIC with vertical coupling
application processors, and graphics the EIC. In addition, for high-speed in FOWLP has been demonstrated
processing units (GPUs) to provide integration, through-silicon vias (TSVs) [4]. The integration of the edge PIC
power-performance-form factor boosts will be required to be used for the PIC remains a big challenge because
that are not obtained by conventional active interposer. The fabrication of the the embedding mold compound is
packaging. A key benefit of advanced TSV on the PIC requires many complex not transparent in the optical signal
w a f e r - l e v e l p a c k a g i n g i s t h e process steps as described in [2]. spect r um, and the optical sig nal
capability to achieve heterogeneous Furthermore, the Si photonics circuit is cannot be coupled from the optical I/
integration whereby ICs from diverse fabricated in a 200mm wafer instead of O at the edge of the PIC after molding.
technologies (complementary metal- a 300mm wafer, which makes the cost The optical I/O is very sensitive to
o x i de s e m i c o n d uc t o r [C M O S ] , of this integration solution unattractive contamination because the optical
SiGe, silicon-on-insulator [SOI], for most commercial applications. The signal has a very short wavelength
PIC, III-V semiconductors, etc.) alternative solution is using various (~1. 3μ m t o ~1. 5μ m), t h e r efo r e ,
ca n be i ndependently opt i m i zed complex customized multiple assembly polishing and cleaning the package
and tightly integrated in small form technologies for the multi-chip module to reveal the PIC edge I/O is very
factor packages to achieve power- integration. However, because of the challenging and time consuming. To
p e r f or m a n c e - f or m fa c t or- c o s t complex assembly requirement and the overcome this problem, the PIC optical
optimization that is not otherwise limited scaling capability, this solution I/O at the edge will be designed with
possible with monolithic integration. is not preferred. an additional silicon buffer section, as

49
Chip Scale Review January • February • 2022 [ChipScaleReview.com] 49