Page 50 - Chip Scale Review_January February_2022-digital

TDP has been increasing ~7%/year and References for signal and power integrity
today has a range between 200W – 300W 1. G. E. Moore, “Cramming more problems in packaging,” IEEE Trans.
for both the CPU and the GPU [12]. The components onto integrated circuits,” on Components, Packaging and
AI chips developed so far have a TDP Electronics, vol. 38, no. 8, pp. 114- Manufacturing Tech., V: 10, Issue: 8,
in the range of 75W-300W and most use 117, 1965. pp: 1276 – 1295, 2020.
engines that accelerate computations in 2. R. H. Dennard, F. H. Gaensslen, H. N. 5. Y. Chen, Y. Xie, L. Song, F. Chen,
conjunction with a CPU or GPU [13]. Yu, V. L. Rideout, E. Bassous, A. R. T. Tang, A Survey of Accelerator
For example, the Tensor Processing Unit LeBlanc, “Design of ion-implanted Architectures for Deep Neural
(TPU) from Google uses HBM combined MOSFETs with very small physical Networks, pub.: Elsevier Engineering,
with CPU for implementing training and dimensions,” IEEE Jour. of Solid- 6, pp. 264 – 274, 2020.
inference engines. With average TDP State Circuits, 9(5), 256-268 (1974). 6. M. O’Connor, “Some highlights of
of 250W and T j =107°C, the effective 3. J. Shalf, “The future of computing the high-bandwidth memory (HBM)
thermal resistance R th required translates beyond Moore’s law,” Philosophical standard,” Proc. Memory Forum
to 0.3°C/W [12]. Achieving such low Trans. of the Royal Soc. A, 378(2166), Workshop, Jun. 14, 2014; https://www.
thermal resistances requires liquid cooling 20190061 (2020). cs.utah.edu/thememoryforum/mike.pdf.
and is a metric that needs to be supported 4. M. Swaminathan, H. M. Torun, H. 7. S. Mukhopadhyay, Y. Long, B.
irrespective of the packaging type used. Yu, J. Ale Hejase, W. D. Becker, Mudassar, C. S. Nair, B. H. DeProspo,
“Demystifying machine learning H. M. Torun, M. Kathaperumal, V.
Smet, D. Kim, S. Yalamanchili and
M. Swaminathan, “Heterogeneous
integration for artificial intelligence:
challenges and opportunities,” IBM
Jour. Res. & Dev., Vol. 63, no. 6, paper
4, 2019.
8. R. Mahajan, et al., “Embedded multi-
die interconnect bridge (EMIB)-
-a high-density, high-bandwidth
packaging interconnect,” 2016 IEEE
66th Elec. Comp. and Tech. Conf.
(ECTC), 2016.
9. A. C. Durgun, Z. Qian, K. Aygun,
R. Mahajan, T. T. Hoang, S. Y.
Shumarayev, “Electrical performance
limits of fine-pitch interconnects for
heterogeneous integration,” IEEE
69th ECTC, pp. 667-673, May, 2019.
10. ANSYS, HFSS. “3D full-wave
electromagnetic field simulation,
ANSYS.,” https://www.ansys.com/
products/electronics/ansys-hfss
11. S. Mueller, K. Z. Ahmed, A. Singh,
A. K. Davis, S. Mukhopadyay, M.
Swaminathan, et al., “Design of
high-efficiency integrated voltage
regulators with embedded magnetic
core inductors,” IEEE 66th ECTC,
E-Tec Interconnect AG, Mr. Pablo Rodriguez, Lengnau Switzerland pp. 566-573.
Phone : +41 32 654 15 50, E-mail: p.rodriguez@e-tec.com 12. L. T. Su, S. Naffziger, M. Papermaster,
“Multi-chip technologies to unleash
computing performance gains over
the next decade,” IEDM, 2017.

Biographies
Madhavan Swaminathan is John Pippin Chair in Microsystems Packaging and Director - 3D Systems Packaging
Research Center (PRC) Georgia Institute of Technology, Atlanta, GA. Email: madhavan@ece.gatech.edu

Siddharth Ravichandran is a recent PhD graduate from the School of Electrical and Computer Engineering at
Georgia Institute of Technology, Atlanta, GA.

48
48 Chip Scale Review January • February • 2022 [ChipScaleReview.com]