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Figure 3: Chiplet interface specification requirements for industry scale adoption.
a monolithically-integrated alternative can be individually, comprehensively, communication latencies and improving
(due to die size-based yield or reticle and efficiently tested prior to assembly system performance.
size limitations, intellectual property together with a chiplet interconnect and In production systems and supply
portability/suitability considerations, packaging integration approach that chains, any additions to cycle time
development cost challenges to achieve enables efficient and comprehensive post- (processing and/or transit times) or
all the required configuration variations, assembly testing with an adequate degree supply chain uncertainty will often
etc.). Still, chiplets are not necessarily of redundancy and repair can help mitigate require additional inventory to be carried.
going to be economically optimal in cases this disadvantage. Likewise, not all chiplet Purchasing external chiplets typically
where a single “sweet spot” monolithic solutions will necessarily require the incurs margin stacking and additional
alternative is feasible and attractive. high bandwidth densities that advanced inventory carrying costs. The use of a
Continuing advances in packaging and packaging can provide, so ideally, the common set of chiplets in many chip
interconnect technology will help reduce chiplet interconnect selected can support configurations can mitigate the impact
tiling overheads over time. For example, an option to use conventional low-cost 2D of these considerations by enabling
Intel’s Foveros Omni is projected to “standard package trace” packaging when inventory pooling. Likewise, consignment
support bump pitches down to 25µm that is economically optimal. arrangements can help mitigate some of
and Intel’s Foveros Direct is projected to Thermal and mechanical constraints the margin stacking and carrying cost
support bump pitches of 10µm or less. can also strongly influence system-level impacts.
Each N-fold improvement in bump pitch partitioning. It is often impractical to While 3D stacking can provide
and wire density scaling for advanced co-package multiple “hot” die together substantial savings in board space,
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packaging potentially enables an N when doing so exceeds the thermal interface density, and power efficiency,
improvement in bandwidth density. capabilities of the resulting system. This chiplets built to be 3D stacked with
Likewise, as process technology improves limitation can be especially severe in other chiplets have historically needed
and connection distance shrinks, we can those industrial or far-edge usages that to be carefully co-designed (e.g., due to
reduce the voltages chiplet interfaces cannot rely on forced-air cooling. It is thermal, power delivery, signal integrity,
use to further improve energy efficiency. likewise similarly impractical to co- etc., considerations), hindering the ability
Chiplet interconnects should therefore, package die that each require a lot of to reuse them in other contexts. However,
ideally, use a “many wires, simple external PCB connectivity because doing as HBM memory has illustrated, we
I/O” philosophy rather than a SerDes-like so will increase package-level and PCB can usefully specify a standard 2D/2.5D
“few wires and complex I/O” approach routing requirements and associated interface to a 3D stack of chiplets that is
to take better advantage of upcoming costs. Instead, it is generally preferable supplied as an integrated subassembly.
improvements in connectivity technology. to co-package functions that require This consideration is a key reason
A more subtle disadvantage of using high-bandwidth connectivity between why it is preferable to initially focus
chiplets is that packaging, assembly, and themselves to take full advantage of multivendor standardization efforts on
test costs and durations will generally the previously noted 10x improvements 2D and 2.xD chiplet connectivity usages
be higher for multi-die chips than in connection density and energy before attempting to standardize 3D
monolithic chips. Using chiplets that efficiency while incrementally reducing interface details.

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